74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 is an 8-bit serial-in, parallel-out shift register with a second 8-bit storage register and three-state output drivers. Serial data enters through DS, advances one position on each rising edge of SHCP, and reaches the parallel outputs only when a rising edge on STCP transfers the completed byte into the storage register.

The separate shift and storage clocks are the feature that makes the device useful for output expansion. A microcontroller can load eight new bits while Q0 through Q7 continue driving the previous word. One STCP edge then updates all eight outputs together. Three controller signals-data, shift clock and storage clock-are therefore enough for eight outputs, and additional devices can be cascaded without adding another data pin.

What Is Inside a 74HC595?

The device contains three functional sections. The first is an 8-stage shift register that samples DS on rising SHCP edges. The second is an 8-bit storage register loaded on a rising STCP edge. The third is a bank of eight three-state drivers controlled by OE̅. Q7S is taken from the final shift stage and provides the serial data needed to extend the chain.

The word "latch" appears in many 74HC595 descriptions, although the storage section is updated by an edge rather than remaining transparent for an enable level. The timing distinction is covered in the latch-versus-flip-flop comparison. The wider relationship between storage, feedback and controlled data transfer is also described in the latch circuit reference.

74HC595 Pinout and Signal Functions

The familiar 16-pin pinout is shared by many HC and HCT implementations, but the exact package drawing and signal notation should always be checked for the selected manufacturer. Nexperia commonly uses DS, SHCP, STCP, MR̅, OE̅ and Q7S. Texas Instruments uses SER, SRCLK, RCLK, SRCLR̅, OE̅ and QH′ for the corresponding signals.

For a basic always-enabled circuit, MR̅ is normally pulled or tied HIGH and OE̅ is tied LOW. Direct ties are acceptable only when the system never needs blanking, bus release or controlled startup. Inputs driven by a microcontroller can be unsafe during reset if its pins become high impedance, so pull resistors may still be required to establish known levels.

How Data Moves Through the 74HC595

Assume the shift register is initially zero and eight bits are sent most-significant bit first. The first transmitted bit enters stage Q0 on the first SHCP rising edge, then moves one stage toward Q7 on every later edge. After eight clocks, the first transmitted bit has reached Q7 and the last transmitted bit occupies Q0. A different software bit order changes the relationship between the byte value and the physical output pins; it does not change the internal shift direction.

1. Hold MR̅ HIGH and OE̅ at the desired output state.
2. Keep STCP from making a rising transition while the new word is being shifted.
3. Set DS to the next bit and allow it to settle before SHCP rises.
4. Pulse SHCP HIGH and LOW once for each bit.
5. After the final shift edge and the required separation time, apply one rising edge to STCP.
6. Q0–Q7 change after the STCP-to-output propagation delay.

SHCP and STCP Are Separate Clock Domains Inside the Device

Both inputs are positive-edge triggered, but they perform different operations. SHCP moves the serial pipeline by one bit. STCP copies a complete internal snapshot to the output register. Keeping the signals separate gives the controller a clean update boundary and prevents intermediate shift states from appearing at the load.

The final SHCP edge and the STCP edge should not be placed arbitrarily close together. The shift-register contents need time to settle before the storage register captures them. As one concrete reference, the TI SN74HC595 timing table at VCC = 4.5 V specifies a 19 ns minimum SRCLK-rising-to-RCLK-rising setup interval across the SN74HC595 operating range. It also guarantees 25 MHz clock operation and specifies 20 ns minimum clock HIGH and LOW pulse widths plus 25 ns SER setup time under that condition. Values differ with supply voltage, load, temperature, manufacturer and logic-family revision.

SHCP and STCP can be tied together in applications that accept a one-clock pipeline relationship. In that configuration, the shift register remains one clock ahead of the storage register. Most microcontroller output-expansion circuits keep them separate because a dedicated STCP signal provides an explicit, glitch-controlled parallel update.

MR̅ and OE̅ Solve Different Problems

Pulling MR̅ LOW immediately clears the eight shift stages. It does not directly erase the storage register. If Q0–Q7 currently display a nonzero word, that word stays present while OE̅ is LOW until STCP rises and copies the cleared shift register into storage.

Driving OE̅ HIGH disconnects Q0–Q7 electrically by placing them in the high-impedance state. The shift and storage registers keep their data. OE̅ can blank a display, release a shared bus or hold external loads inactive during startup, but it cannot substitute for loading a safe output word.

74HC595 Operating Video

Video: "The Shift Register: Explained [74HC595]" by electronica.

74HC595 Output Current: Use the Guaranteed Logic Levels

Output-current design starts with the VOH and VOL tables, not the absolute maximum section. Current drawn from a HIGH output lowers VOH; current sunk by a LOW output raises VOL. The load must still receive a valid voltage after that drop, and the total current through the package supply pins must remain within its limit.

For example, TI specifies its SN74HC595 parallel outputs at approximately ±6 mA with VCC = 4.5 V while maintaining guaranteed output levels. The same data sheet lists ±35 mA continuous current for one output and ±70 mA through VCC or GND under absolute maximum ratings. Those larger figures are stress limits. Continuous operation near them is outside the recommended design conditions and leaves no useful logic-level, thermal or simultaneous-switching margin.

Choosing LED Resistors

Every LED needs its own series resistor. For a LOW-side connection in which the 74HC595 sinks current, a first calculation is:

For a HIGH-side connection in which the output sources current, use the guaranteed loaded VOH rather than assuming that the output remains exactly at VCC:

After choosing a resistor, check every simultaneously illuminated channel against the total device current and package dissipation. Multiplexed displays also require peak-current and duty-cycle calculations. Relays, solenoids, motors, high-current lamps and large LED arrays need external transistor or MOSFET drivers, flyback protection where inductance is present, and a supply path sized for the load.

3.3 V and 5 V Logic Compatibility

A 74HC595 powered at 3.3 V is normally straightforward to drive from a 3.3 V microcontroller when both devices share a valid ground and the selected part supports that supply. Q0–Q7 then produce approximately 3.3 V logic levels, subject to output loading.

A 74HC595 powered at 5 V has CMOS input thresholds that scale with VCC. The TI SN74HC595, for example, specifies VIH = 3.15 V minimum at VCC = 4.5 V. A nominal 3.3 V microcontroller output leaves little margin after tolerance, noise and voltage drop, and a guaranteed interface cannot be assumed across all HC vendors and conditions.

Three common solutions are available:

• Power the HC device from 3.3 V if the loads accept 3.3 V output levels.
• Use a 74HCT595 at approximately 5 V when TTL-compatible input thresholds suit the controller interface.
• Insert a level translator when voltage domains, edge quality or power sequencing require explicit isolation.

Input overvoltage tolerance and clamp structures vary between logic families and manufacturers. A series resistor does not automatically make every HC595 input safe at a voltage above VCC. Verify the input-voltage rating, injection-current limit and power-off behavior of the exact part.

Cascading Multiple 74HC595 Devices

Connect Q7S of the first device to DS of the second. Share SHCP and STCP across the chain. MR̅ and OE̅ may also be shared when every device must clear or release its outputs together. A chain of N devices requires 8N shift-clock edges before a single STCP edge updates all outputs.

The formula covers bit transfer only. Firmware overhead, STCP pulse timing and the required setup interval add to the update time. Long chains also increase clock-line capacitance and make Q7S propagation delay, trace ringing, ground bounce and connector quality more important.

There is no universal maximum device count. The practical limit is reached when the controller cannot shift the required word within the update interval, the last Q7S-to-DS path violates setup time, or clock and supply integrity no longer meet the data-sheet conditions. Buffering a heavily loaded clock, slowing the edge rate with a carefully selected source resistor, improving ground return and distributing decoupling are more useful than relying on an arbitrary chain-length rule.

SPI Connection

Hardware SPI can drive the serial path efficiently. Connect MOSI to DS and SCK to SHCP, then use a separate GPIO for STCP. Select a mode in which MOSI is stable before the rising SCK edge; SPI mode 0 is a common choice. OE̅ and MR̅ can be fixed at safe levels or assigned to extra GPIOs when blanking and hardware clear are required.

set_output_enable(HIGH);     // Q0-Q7 high impedance during startup
set_master_reset(LOW);      // clear the shift register
wait_minimum_reset_pulse();
set_master_reset(HIGH);
pulse_storage_clock();      // transfer zeros into output storage
set_output_enable(LOW);     // drive the known all-zero word

spi_write(next_output_byte); // DS is sampled on each SHCP rising edge
wait_required_clock_spacing();
pulse_storage_clock();       // update all eight outputs together

The bit order must match the board net names. If software sends the most-significant bit first, the first bit normally ends at Q7 after eight shifts and the final bit remains at Q0. A one-hot walking-bit test is the quickest way to verify physical mapping before loads are energized.

Power, Layout and Startup Design

• Place a 100 nF ceramic capacitor close to VCC and GND for each 74HC595. The connection loop should be short and should not share a narrow return path with high-current loads.
• Give SHCP and STCP continuous ground references. Fast logic edges can ring even when the nominal clock frequency is modest.
• Hold MR̅, OE̅, SHCP and STCP at defined levels while the controller is resetting. Floating CMOS inputs can cause extra clock edges and unpredictable outputs.
• Keep OE̅ HIGH during power-up when external loads must remain inactive, then clear and latch a known word before enabling the outputs.
• Route inductive or high-current load return current away from the logic ground path. External drivers should include the protection required by the load.
• For cables or long board traces, verify edge integrity at the receiving pins with an oscilloscope. Count threshold crossings rather than judging only the apparent clock frequency.

Common 74HC595 Applications and Their Limits

74HC595, 74HCT595 and Other Shift Registers

Nexperia lists 74HC595 and 74HCT595 options in SO16, TSSOP16 and leadless packages. Aetrix product pages include the 74HC595D,118 in SO16, 74HC595PW,118 in TSSOP16 and 74HC595BQ,115 in DHVQFN16. Package code, temperature grade, packing suffix and qualification status belong to the complete orderable number and should be checked independently.

The broader shift-register category includes serial-to-parallel and parallel-to-serial devices with different control structures. Parts that share "8-bit shift register" in their descriptions are not automatically pin-compatible or functionally equivalent.

Troubleshooting Common 74HC595 Problems

Package and Procurement Checks

A complete 74HC595 order review should include manufacturer, logic family, package drawing, temperature range, qualification, tape orientation and packing suffix. HC, HCT, AHC, AHCT, LV and LVC versions can differ in supply range, thresholds, speed, overvoltage behavior and output drive even when their functional block diagrams look similar.

• Match the land pattern to the exact package drawing; SO16, TSSOP16 and DHVQFN16 footprints are not interchangeable.
• Confirm whether automotive qualification is required instead of assuming that a −40 °C to +125 °C rating establishes qualification.
• Check the manufacturer's lifecycle status for the exact suffix, not only the generic 74HC595 family name.
• For cross-manufacturer replacement, compare VIH/VIL, VOH/VOL at load, timing limits, pin functions, power-off behavior and package dimensions.
• Use traceability, packaging inspection and electrical testing appropriate to the sourcing channel and application risk.

For production quantities or a multi-manufacturer comparison, submit the full part number, package, required temperature range and annual demand through the Aetrix RFQ page. Those details prevent a functionally similar device in the wrong logic family or footprint from being treated as a direct substitute.

Technical References

• Nexperia 74HC595 / 74HCT595 product and application data
• Texas Instruments SN54HC595 / SN74HC595 data sheet
• Nexperia products at Aetrix Electronics

Frequently Asked Questions

What is a 74HC595 used for?

It converts serial data into eight stable parallel outputs. Common uses include status LEDs, display segments, chip-select banks and write-only microcontroller output expansion.

How many microcontroller pins does one 74HC595 require?

Basic operation requires three signals: DS for data, SHCP for shifting and STCP for the parallel update. OE̅ and MR̅ may be tied to defined levels or controlled with additional pins.

What is the difference between SHCP and STCP?

SHCP shifts one serial bit on each rising edge. STCP copies all eight shift-register bits into the storage register on its rising edge, causing Q0–Q7 to update together.

Does MR̅ immediately clear the 74HC595 outputs?

No. MR̅ clears the shift register asynchronously. The cleared zeros reach Q0–Q7 only after a rising STCP edge transfers them to the storage register, assuming OE̅ is LOW.

Can a 3.3 V microcontroller drive a 5 V 74HC595?

It is not guaranteed for every HC implementation. Compare the controller's minimum VOH with the 74HC595 VIH requirement. A 3.3 V-powered HC device, a 5 V HCT device with TTL-compatible inputs or a level translator may provide a valid interface.

Can the 74HC595 drive eight LEDs directly?

It can drive low-current LEDs when each LED has a resistor and all per-output, total-current, output-voltage and package-power limits are satisfied. High-current LEDs and multiplexed arrays usually require external drivers.

How many 74HC595 devices can be cascaded?

The logic architecture sets no small fixed count. The practical limit depends on the required update rate, Q7S propagation delay, next-device setup time, clock loading, signal integrity, supply distribution and PCB or cable length.

What is the difference between 74HC595 and 74HC164?

The 74HC595 has a separate output storage register and three-state parallel drivers, so outputs can remain stable while a new word shifts in. The 74HC164 exposes its shifting states at the parallel outputs and does not provide the same atomic update.