Cypress Semiconductor Corp CY14B104NA-ZS20XI

Overview

CY14B104NA-ZS20XI from Cypress Semiconductor is a 4-Mbit non-volatile SRAM (nvSRAM) with 256K × 16 organization, 20 ns access time, single 3 V (+20%, –10%) supply, and QuantumTrap non-volatile storage technology. It performs automatic STORE on power-down using an external VCAP capacitor and supports software- or hardware-initiated STORE/RECALL. Used in industrial control systems requiring persistent memory without battery backup.

For engineers reviewing the CY14B104NA-ZS20XI datasheet, CY14B104NA-ZS20XI pinout, CY14B104NA-ZS20XI application, or CY14B104NA-ZS20XI equivalent, key selection criteria include ×16 bus interface support, HSB-controlled hardware STORE capability, AutoStore timing compliance (tDELAY, tHHHD), and FBGA/TSOP II package compatibility for space-constrained embedded designs.

Technical Context

The CY14B104NA-ZS20XI integrates standard SRAM array (256K × 16) with parallel QuantumTrap non-volatile cells per bit, enabling simultaneous STORE/RECALL across all locations. Its architecture decouples volatile read/write (infinite cycles) from non-volatile STORE (1 million cycles) and RECALL (infinite cycles).

AutoStore triggers when VCC drops below VSWITCH, disconnecting VCAP to supply STORE energy; HSB serves dual role - input to initiate hardware STORE and open-drain output signaling busy state. Byte enables BHE/ BLE enable selective 16-bit word writes, and CE/OE/WE timing complies with standard SRAM protocols (tAA = 20 ns, tACE ≤ 20 ns).

Key Specifications

Pinout & Package

Package: 48-ball fine-pitch ball grid array (FBGA), RoHS-compliant, 7 mm × 9 mm footprint. Pinout validated per Cypress Document 001-49918 Rev. *O (Page 3, Figure 1) for ×16 configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar non-volatile SRAM applications.

Compared with FM24V10-G and MB85RS4MT, the CY14B104NA-ZS20XI uniquely delivers hands-off AutoStore using passive VCAP energy harvesting - eliminating firmware dependency and interrupt latency while maintaining full SRAM timing transparency.

Availability

CY14B104NA-ZS20XI is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostic devices, telecom infrastructure, and automotive ADAS ECUs requiring stable component supply with guaranteed long-term lifecycle support.

Supply support for CY14B104NA-ZS20XI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-reliability memory and programmable solutions for industrial, automotive, and communications markets.

The CY14B nvSRAM product line targets applications needing instant-on, battery-free non-volatility - specifically engineered for deterministic STORE/RECALL in mission-critical embedded systems with strict power-loss response requirements.

FAQ

Is CY14B104NA-ZS20XI pin-compatible with CY14B104LA?

No. CY14B104NA is organized as 256K × 16 with BHE/ BLE pins and uses A0–A17 addresses; CY14B104LA is 512K × 8 with A0–A18 and no byte enables. Their pinouts differ significantly - especially in FBGA and TSOP II packages - and require separate PCB layouts.

What happens if the VCAP capacitor is omitted?

Omitting the 0.1 µF VCAP capacitor disables AutoStore functionality. The device will not perform automatic STORE on power-down and may corrupt data if AutoStore is enabled without VCAP. Software or hardware STORE must then be used exclusively, requiring active system intervention before power loss.

Does CY14B104NA-ZS20XI support both ×8 and ×16 configurations?

No. CY14B104NA is fixed at 256K × 16 organization with DQ0–DQ15 and BHE/ BLE pins. The ×8 variant is the CY14B104LA (512K × 8). The "NA" suffix explicitly denotes the 16-bit data bus configuration and is not configurable via strap pins or mode registers.

Can HSB be left unconnected in systems not using hardware STORE?

Yes. HSB may be left floating or tied HIGH via pull-up if hardware STORE is unused. However, it must not be driven LOW externally unless initiating STORE, and its status should still be monitored during AutoStore to avoid concurrent SRAM access - per datasheet timing constraint tLZHSB.