Infineon Technologies CY7C60123-PXC

Overview

CY7C60123-PXC from Infineon Technologies (formerly Cypress) is an enCoRe™ II LV low-voltage 8-bit flash microcontroller with Harvard architecture, 8 KB flash, 256 bytes RAM, and operating voltage of 2.7–3.6 V. It features up to 36 GPIO pins, dual 8-bit capture timers for RF edge timing, and internal crystalless oscillator-designed for wireless HID devices such as optical mice and remote controls.

For engineers reviewing the CY7C60123-PXC datasheet, CY7C60123-PXC pinout, CY7C60123-PXC application, or CY7C60123-PXC equivalent, key selection criteria include its 12 MHz M8C CPU speed, 5 µA sleep current, programmable 8/50 mA sink per designated I/O pin, SPI master/slave support up to 2 Mbps, and integrated wakeup timer eliminating external components.

Technical Context

The CY7C60123-PXC implements a Harvard-architecture M8C core with on-chip 12 MHz internal oscillator, configurable for crystal/resonator/clock input. Its dual 8-bit capture timer registers (TIO0/P0.5 and TIO1/P0.6) independently store rising/falling edge timestamps from the 16-bit free-running timer, enabling precise RF signal demodulation in wireless receivers.

GPIO ports are partitioned: Ports 0–1 support per-pin configuration including maskable interrupts and programmable drive strength (2 mA source / 8 or 50 mA sink); Ports 2–4 operate as byte/nibble groups. The device integrates LVD with user-selectable threshold, watchdog timer, and POR circuit sharing one interrupt vector.

Key Specifications

Pinout & Package

Package: 40-pin plastic dual inline package (PDIP).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-voltage 8-bit microcontroller applications.

Compared with STM8L052C6T6 and PIC16F15323-I/SL, the CY7C60123-PXC delivers deterministic sub-microsecond edge capture timing essential for IR/RF protocol decoding, while maintaining lower active power than the STM8L and simpler register-level compatibility than the PIC for legacy enCoRe II codebases.

Availability

CY7C60123-PXC is available at Aetrix Electronics and suitable for optical mouse control, IR remote receivers, wireless presenter tools, and POS terminal keypad interfaces requiring stable component supply across industrial and consumer electronics production cycles.

Supply support for CY7C60123-PXC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a global semiconductor leader headquartered in Munich, Germany, specializing in power management, automotive, industrial, and security solutions.

The enCoRe™ II LV product line was developed by Cypress (acquired by Infineon in 2020) specifically for cost-sensitive, battery-operated human interface devices requiring integrated timing, low-power operation, and minimal external components.

FAQ

What is the maximum operating frequency of the M8C CPU in CY7C60123-PXC?

The M8C CPU operates at up to 12 MHz when driven by the internal oscillator or an external clock source. This frequency is fixed and not adjustable via software; it defines the instruction cycle timing and directly impacts SPI transfer rates, timer resolution, and interrupt latency. External crystals up to 24 MHz may be used, but the CPU clock is derived via internal prescaling and remains capped at 12 MHz.

Does CY7C60123-PXC support in-system programming (ISP) without high-voltage signals?

Yes, CY7C60123-PXC supports in-system serial programming (ISSP) using only VDD, GND, SCLK (P1.0), and SDATA (P1.1) at standard I/O voltage levels - no high-voltage programming signal is required. The ISSP interface is active upon power-up when specific pin states are detected, enabling field firmware updates through a simple 4-wire connection without removing the device from the PCB.

How does the dual capture timer function differ from a standard input capture peripheral?

Unlike standard input capture modules that store only one edge timestamp per event, CY7C60123-PXC's dual capture timer uses two independent 8-bit registers - one for rising edges and one for falling edges - both tied to the same free-running timer base. This allows simultaneous, non-overlapping capture of pulse width and period in a single hardware cycle, eliminating firmware overhead for edge discrimination and enabling accurate duty-cycle measurement in IR/RF carrier decoding.

Can all 36 GPIO pins be used simultaneously in a 40-pin PDIP package?

No - the 40-pin PDIP package exposes 34 GPIO-capable pins (P0.0–P0.7, P1.0–P1.7, P2.0–P2.7, P3.0–P3.7, P4.0–P4.3). Two pins (pins 7 and 8 in the 40-pin layout) are NC (no connect). Port 4 has only four pins (P4.0–P4.3), and Port 3 is limited to eight pins (P3.0–P3.7); full 36-pin utilization requires the 48-pin SSOP variant where P4.0–P4.3 and additional P3.x pins are fully routed.