Infineon Technologies CY8C21345-24SXI

Overview

CY8C21345-24SXI from Cypress Semiconductor is a programmable PSoC® 1 System-on-Chip featuring an M8C 8-bit Harvard-architecture CPU running at up to 24 MHz, 16 KB flash, 1 KB SRAM, and integrated analog/digital configurable blocks-including dual 8-bit ADCs, up to eight digital blocks (PWM, timers, UART, SPI), and CapSense®-optimized resources. It operates from 3.0 V to 5.25 V across –40 °C to +85 °C and targets embedded control in human-interface and sensor-conditioning applications.

For engineers reviewing the CY8C21345-24SXI datasheet, CY8C21345-24SXI pinout, CY8C21345-24SXI application, or CY8C21345-24SXI equivalent, key selection criteria include its 24 MHz IMO clock accuracy (±5% over industrial range), 10-bit SAR ADC performance (200 ksps, ±2.5 LSB INL), CapSense® dual-channel scanning capability, and 28-pin SOIC package compatibility with legacy PSoC 1 designs.

Technical Context

The CY8C21345-24SXI implements a fixed-function M8C core with 21-interrupt-vector controller and dedicated system resources including IMO (24/48 MHz), ILO (32 kHz), and optional ECO+PLL for crystal-referenced timing. Its digital system comprises eight 8-bit PSoC blocks configurable as 8–32-bit timers, PWMs with deadband, full-duplex UART, and dual SPI masters/slaves-all routable to any GPIO via global interconnect.

Analog functionality centers on a 10-bit SAR ADC (200 ksps, ±2.5 LSB INL at VDD ≥ 3.0 V) and six Type "E" analog blocks supporting comparators, single/dual 8-bit ADCs, and CapSense® with two IDACs (up to 640 µA), dedicated CSD/CNT clocks, and 16-bit scanning timers-enabling synchronized analog-digital operation via external or digital-block triggers.

Key Specifications

Pinout & Package

Package: 28-pin SOIC (Small Outline Integrated Circuit), 300 mil width, RoHS-compliant, JEDEC MS-012AC standard.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable SoC applications.

Compared with CY8C22345-24SXI and CY8C22545-24PXI, the CY8C21345-24SXI delivers optimal cost/performance balance for touch and sensor-edge applications constrained to 28-pin SOIC, offering full CapSense® and 10-bit ADC capability without over-provisioned resources.

Availability

CY8C21345-24SXI is available at Aetrix Electronics and suitable for touch-control interfaces, industrial sensor nodes, smart lighting modules, and legacy equipment retrofits requiring stable component supply and long-term obsolescence management.

Supply support for CY8C21345-24SXI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in programmable embedded solutions, memory, and connectivity products for industrial, automotive, and consumer markets.

The CY8C21345 belongs to the PSoC® 1 family-designed specifically for cost-sensitive, low-power embedded control applications requiring mixed-signal flexibility, CapSense® integration, and rapid prototyping without custom ASIC development.

FAQ

What is the maximum operating frequency of the M8C core in CY8C21345-24SXI?

The M8C CPU core operates at up to 24 MHz, supported by the internal main oscillator (IMO). This frequency is guaranteed across the full industrial temperature range (–40 °C to +85 °C) with ±5% tolerance; tighter accuracy requires optional 32.768 kHz crystal and PLL configuration.

Does CY8C21345-24SXI support true 10-bit ADC conversion with external reference?

Yes-the integrated 10-bit SAR ADC supports external reference inputs via P2[6]/P2[7] (Vref+ and Vref–), enabling precise measurement against stable external sources. Internal 1.3 V reference is also available, and ADC performance (±2.5 LSB INL) is specified for VDD ≥ 3.0 V and Vref ≥ 3.0 V.

Can CapSense® functionality operate while the device is in low-power sleep mode?

No-CapSense® scanning requires active CPU and analog clock domains. However, the device supports wake-on-touch using GPIO interrupt capability: electrodes can be configured to trigger XRES or interrupt pins upon threshold crossing, allowing ultra-low-power standby with sub-10 µA current draw until touch event occurs.

Is in-system programming (ISSP) supported through standard interfaces like SWD or JTAG?

No-ISSP uses a proprietary two-wire serial protocol (clock + data) implemented via dedicated pins or shared I2C lines (SDA/SCL). It does not support SWD or JTAG; programming requires Cypress-provided MiniProg1/MiniProg3 programmers or compatible third-party tools with ISSP firmware support.