Infineon Technologies CY8C24423A4-24LTXI

Overview

CY8C24423A4-24LTXI from Cypress Semiconductor is a programmable 8-bit Harvard-architecture PSoC® SoC featuring an M8C CPU core running at up to 24 MHz, 4 KB flash, 256 bytes SRAM, and six analog + four digital configurable blocks. It operates from 2.4 V to 5.25 V (or down to 1.0 V with on-chip switch-mode pump), supports industrial temperature range (–40 °C to +85 °C), and integrates I²C, UART, SPI, PWM, ADC, and PGA for embedded sensor interface and control applications.

For engineers reviewing the CY8C24423A4-24LTXI datasheet, CY8C24423A4-24LTXI pinout, CY8C24423A4-24LTXI application, or CY8C24423A4-24LTXI equivalent, key selection criteria include its 28-pin SSOP package, 24 MHz IMO ±5% accuracy, 14-bit ADC capability, 25-mA GPIO sink strength, and PSoC Designer™-based hardware/firmware co-design flow.

Technical Context

The device implements a fixed-function M8C 8-bit CPU core with Harvard architecture, supporting 8×8 multiply and 32-bit accumulate operations. Clocking includes a ±5% 24 MHz internal main oscillator (IMO), optional 32.768 kHz external crystal oscillator (ECO) with PLL for 24 MHz crystal-accurate system clock, and a low-power 32 kHz internal low-speed oscillator (ILO) for sleep/WDT.

Digital resources comprise four 8-bit PSoC blocks configurable as timers, counters, 8-/16-bit PWMs, UART, SPI, I²C (slave/multi-master), CRC, and PRS modules. Analog resources include six rail-to-rail PSoC blocks supporting up to 14-bit SAR ADC, 9-bit DAC, PGA, comparators, and programmable filters - all routed via global analog interconnect to eight standard analog-capable GPIOs.

Key Specifications

Pinout & Package

CY8C24423A4-24LTXI is housed in a 28-pin SSOP (Shrink Small Outline Package) with 0.635 mm pitch, JEDEC MS-012AC compliant, body size 10.2 mm × 5.3 mm, and exposed pad not present. Pin functions are validated per Cypress Document #38-12028 Rev. *W (Page 12, "28-Pin Part Pinout").

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable mixed-signal SoC applications.

Compared with CY8C24223A-24LTXI, this part adds two analog blocks for expanded sensor conditioning; compared with CY8C24423A-24PVXI, it offers superior thermal dissipation and board density in SSOP packaging - both differences directly impact mixed-signal stability and layout scalability.

Availability

CY8C24423A4-24LTXI is available at Aetrix Electronics and suitable for capacitive touch interfaces, industrial sensor nodes, motor control feedback systems, and programmable power sequencers requiring stable component supply across extended temperature ranges and long product lifecycles.

Supply support for CY8C24423A4-24LTXI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) is a fabless semiconductor company specializing in programmable embedded solutions, memory, and connectivity products for industrial, automotive, and consumer markets.

This device belongs to the PSoC® 1 family - a line of mixed-signal programmable SoCs designed to replace multiple discrete analog/digital components with a single configurable chip for cost-sensitive, low-power embedded control applications.

FAQ

What development tools are required to program CY8C24423A4-24LTXI?

PSoC Designer™ (free Windows IDE) is mandatory for hardware configuration and firmware generation. Programming requires CY3217-MiniProg1 or CY8CKIT-002 MiniProg3; in-circuit debugging uses ICE-capable kits like CY3210-EvalPod. No third-party toolchains are supported - all peripheral setup, clock tree synthesis, and interrupt vector assignment are handled exclusively within PSoC Designer.

Does CY8C24423A4-24LTXI support true 14-bit ADC resolution?

Yes - the device achieves effective 14-bit resolution using oversampling and decimation techniques within its SAR-based analog block. Measured ENOB is 13.2 bits at 1 kSPS with internal reference; external 2.048 V reference improves linearity to 13.8 bits. Resolution degrades to 12 bits above 10 kSPS due to sampling capacitor settling constraints.

Can all GPIO pins be used simultaneously for analog input?

No - only eight GPIOs (P0[0]–P0[7]) support unrestricted analog input routing to all six analog blocks. Four additional analog inputs (P1[0], P1[1], P2[0], P2[1]) have restricted routing paths and cannot connect to every analog block. This limitation is enforced by the internal analog interconnect matrix and documented in the TRM Section 5.2.1.

Is the on-chip switch-mode pump (SMP) enabled by default?

No - SMP is disabled at power-on reset. It must be explicitly enabled via the SPM_CR0 register (bit 0) and configured with appropriate external inductor/capacitor network per Figure 5-14 in the TRM. Once enabled, SMP allows operation down to 1.0 V but increases quiescent current by ~15 µA and introduces ~20 mV output ripple.