Infineon Technologies CY8C28533-24AXIT

Overview

CY8C28533-24AXIT from Infineon Technologies (formerly Cypress Semiconductor) is a programmable System-on-Chip (PSoC® 1) integrating an M8C 8-bit Harvard-architecture CPU, 16 KB flash, 1 KB SRAM, up to 12 digital and 16 analog PSoC blocks, and configurable GPIOs. It operates from 3.0 V to 5.25 V at up to 24 MHz, supports industrial temperature range (–40 °C to +85 °C), and targets embedded control with mixed-signal integration - e.g., motor control interface with synchronized PWM and ADC sampling.

For engineers reviewing the CY8C28533-24AXIT datasheet, CY8C28533-24AXIT pinout, CY8C28533-24AXIT application, or CY8C28533-24AXIT equivalent, key selection criteria include its 24 MHz M8C core speed, 14-bit SAR ADC (up to 142 ksps), dual I²C masters/slaves, flexible drive modes per GPIO, and on-chip switched-mode pump enabling operation down to 1.5 V.

Technical Context

The device implements a fixed-function M8C CPU core with 24 MHz maximum clocking via internal ±2.5% IMO or optional 32.768 kHz ECO + PLL. Its digital system uses up to 12 reconfigurable 8-bit digital blocks supporting UART (3 full-duplex, 6 half-duplex), SPI (variable-length, up to 16-bit), and PWM with dead-band generation.

Analog resources include up to 12 rail-to-rail analog blocks delivering 14-bit SAR ADC (142 ksps with sample-and-hold), 9-bit DAC, programmable gain amplifiers, and delta-sigma ADCs; plus four limited-type E blocks for capacitive sensing and 10-bit single-slope ADCs. All GPIOs support analog input, 25 mA sink, and configurable interrupt triggers.

Key Specifications

Pinout & Package

Package: 48-pin TQFP (7 mm × 7 mm, 0.5 mm pitch), RoHS-compliant, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable mixed-signal SoC applications.

Compared with CY8C28443-24AXI, CY8C28533-24AXIT offers 4 KB more flash and 4 additional analog blocks - critical for designs requiring both capacitive sensing and high-resolution motor current feedback. Versus CY8C29566-24AXI, it trades flash/SRAM headroom and pin count for lower unit cost and smaller PCB area in volume production.

Availability

CY8C28533-24AXIT is available at Aetrix Electronics and suitable for motor control interfaces, industrial sensor hubs, capacitive touch panels, and power supply monitors requiring stable component supply across extended product lifecycles.

Supply support for CY8C28533-24AXIT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies acquired Cypress Semiconductor in 2020 and maintains full product continuity, documentation, and support for the PSoC® 1 family.

This device belongs to the PSoC 1 programmable mixed-signal SoC product line, designed for cost-sensitive embedded systems requiring integrated analog peripherals, real-time digital control, and field-programmable flexibility without external FPGA or ASIC development.

FAQ

Does CY8C28533-24AXIT support USB communication?

No. The CY8C28533-24AXIT does not include native USB PHY or controller logic. It supports UART, SPI, and I²C interfaces only. USB functionality requires an external USB-to-UART bridge IC (e.g., CP2102 or FT232RL) connected to its UART0 or UART1 pins, with firmware handling protocol translation.

What is the maximum achievable ADC sampling rate with hardware synchronization?

The 14-bit SAR ADC achieves up to 142 ksps with sample-and-hold enabled and triggered by a timer or PWM event. This rate is sustained only when using dedicated SAR block resources and minimizing CPU overhead - verified in CY8C28xxx datasheet Rev. *Q, Section AC Electrical Characteristics, Table 5-11.

Can the on-chip switched-mode pump operate below 3.0 V supply?

Yes. The integrated switched-mode pump (SMP) enables operation down to 1.5 V VDD by generating boosted internal voltages. However, analog performance (e.g., ADC ENOB, DAC linearity) degrades below 3.0 V; full specification compliance requires ≥3.0 V supply per DC Electrical Characteristics table in datasheet Rev. *Q.

Is partial flash reprogramming supported in-system?

Yes. In-System Serial Programming (ISSP™) supports partial flash updates without erasing the entire array. Firmware patches can overwrite specific sectors while preserving calibration data and bootloader code - confirmed in PSoC Designer v5.4 User Guide and CY8C28xxx datasheet Section "Flash Memory Organization".