Infineon Technologies CY8C28545-24AXI

Overview

CY8C28545-24AXI from Infineon Technologies (formerly Cypress Semiconductor) is a programmable System-on-Chip (PSoC® 1) integrating an M8C 8-bit Harvard-architecture microcontroller, up to 12 digital PSoC blocks, up to 16 analog PSoC blocks, 16 KB flash, 1 KB SRAM, and configurable GPIOs - all operating at up to 24 MHz with 3.0–5.25 V supply and industrial –40 °C to +85 °C temperature range. It targets embedded control applications requiring mixed-signal reconfigurability, such as capacitive sensing interfaces and multi-channel data acquisition.

For engineers reviewing the CY8C28545-24AXI datasheet, CY8C28545-24AXI pinout, CY8C28545-24AXI application, or CY8C28545-24AXI equivalent, key selection criteria include its 24 MHz M8C core speed, 14-bit SAR ADC (up to 142 ksps), dual I²C resources, 25 mA sink capability per GPIO, and support for on-chip switched-mode pump enabling operation down to 1.5 V.

Technical Context

The CY8C28545-24AXI implements a fixed-function M8C CPU core with Harvard architecture, executing instructions from 16 KB on-chip flash and storing data in 1 KB SRAM. Its clock system includes a ±2.5% accurate 24 MHz internal main oscillator (IMO), a 32.768 kHz external crystal oscillator (ECO) option for RTC, and a low-power internal low-speed oscillator (ILO) for watchdog and sleep timing.

Digital peripherals are built from up to 12 reconfigurable 8-bit digital PSoC blocks, supporting UART (up to 3 full-duplex), SPI (variable-length masters/slaves), PWM (8-/16-bit with dead-band), timers/counters (8–32 bit), and CRC/PRS modules. Analog functionality derives from up to 16 analog blocks - including dedicated SAR ADCs, delta-sigma ADCs, PGAs, comparators, and capacitive sensing engines - all routed via global analog interconnect.

Key Specifications

Pinout & Package

Package: 44-pin TQFP (7 mm × 7 mm, 0.8 mm pitch), RoHS-compliant, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable mixed-signal controller applications.

Compared with CY8C28445-24AXI, the CY8C28545-24AXI adds four analog blocks enabling dual high-speed ADC channels or enhanced CapSense resolution; versus CY8C28645-24AXI, it trades two digital blocks for lower unit cost while retaining full analog feature parity - making it optimal for analog-intensive, communication-light designs.

Availability

CY8C28545-24AXI is available at Aetrix Electronics and suitable for industrial motor control, capacitive touch interfaces, smart sensor nodes, and programmable power monitors requiring stable component supply and long-term manufacturability.

Supply support for CY8C28545-24AXI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a global semiconductor leader headquartered in Munich, Germany, specializing in power management, automotive, industrial, and IoT solutions.

This device belongs to the PSoC® 1 family - Infineon's legacy programmable mixed-signal SoC platform designed for cost-sensitive, low-to-mid complexity embedded control applications where analog configurability and rapid prototyping are essential.

FAQ

What development tools are required to program and debug CY8C28545-24AXI?

PSoC Designer™ (free Windows IDE) is the official development environment, supporting drag-and-drop peripheral configuration, API generation, and C code integration. Programming and debugging require MiniProg3 or compatible ISSP programmers; full-speed emulation and 128 KB trace memory are supported. No JTAG adapter is needed - SWDCK/SWDIO pins provide native in-circuit debug access.

Does CY8C28545-24AXI support true hardware PWM with dead-band insertion?

Yes - its digital PSoC blocks can be configured as 8- or 16-bit PWMs with programmable dead-band generation, kill input, and synchronization across multiple channels. This is implemented in dedicated hardware logic, not firmware-timed GPIO toggling, ensuring deterministic timing and jitter-free output for motor gate drivers.

Can the on-chip 14-bit SAR ADC operate simultaneously with the delta-sigma ADCs?

No - the CY8C28545-24AXI includes either SAR or delta-sigma ADC capability depending on analog block allocation, but not both concurrently. The device has up to 16 analog blocks, and SAR and delta-sigma functions occupy mutually exclusive block types; users must choose one architecture per design based on speed vs. resolution trade-offs.

Is the switched-mode pump (SMP) enabled by default, and what is its output voltage?

The SMP is disabled by default at power-on and must be explicitly enabled in firmware. When active, it generates a regulated ~1.5 V output from the VDD supply, powering internal analog circuitry to maintain performance at reduced system voltage - enabling operation down to 1.5 V VDD while preserving ADC linearity and comparator thresholds.