Infineon Technologies CY8C5468LTI-037

Overview

CY8C5468LTI-037 from Infineon Technologies (acquired Cypress Semiconductor) is a programmable system-on-chip (PSoC® 5) integrating a 32-bit ARM Cortex-M3 CPU, dual 12-bit SAR ADCs (700 ksps), four 8-bit DACs (5.5 Msps), 24 UDBs, and full-speed USB 2.0, in a 68-pin QFN package rated for –40 °C to +85 °C industrial operation. It serves as a configurable mixed-signal controller for embedded signal acquisition and real-time control.

For engineers reviewing the CY8C5468LTI-037 datasheet, CY8C5468LTI-037 pinout, CY8C5468LTI-037 application, or CY8C5468LTI-037 equivalent, key selection criteria include its 67 MHz CPU clock, 256 KB flash/64 KB SRAM memory hierarchy, 46 GPIOs with analog routing capability, low-power hibernate mode (300 nA), and integrated DFB for FIR/IIR filtering without CPU load.

Technical Context

The CY8C5468LTI-037 implements a hierarchical mixed-signal architecture: its ARM Cortex-M3 core executes firmware while offloading signal processing to dedicated hardware-dual SAR ADCs feed data directly to the 24-bit digital filter block (DFB) via DMA, enabling real-time filtering at up to 67 MHz. Analog signal paths are routed through a programmable analog interconnect supporting PGA, TIA, and mixer configurations within SC/CT blocks.

Digital flexibility stems from 24 universal digital blocks (UDBs), each combining PLD logic and state machines, enabling custom peripherals like quadrature decoders or CRC engines; routing is fully configurable between any GPIO and any analog/digital peripheral, including USBIO pins supporting full-speed USB 2.0 physical layer operation with external 24 MHz crystal.

Key Specifications

Pinout & Package

Package: 68-pin QFN (10 mm × 10 mm, 0.5 mm pitch), exposed thermal pad, RoHS-compliant, industrial temperature grade (–40 °C to +85 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable mixed-signal controller applications.

Compared with STM32F303VCT6 and PSoC™ 62S2-064DXI, CY8C5468LTI-037 uniquely combines full-speed USB 2.0 with a hardware DFB and fully configurable analog blocks - making it optimal for applications demanding integrated signal acquisition, real-time filtering, and PC connectivity in a single chip.

Availability

CY8C5468LTI-037 is available at Aetrix Electronics and suitable for industrial sensor hubs, medical wearables, smart home touch interfaces, and USB-capable PLC modules requiring stable component supply across extended product lifecycles.

Supply support for CY8C5468LTI-037 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies acquired Cypress Semiconductor in 2020 and now manufactures and supports the PSoC® family, delivering high-reliability semiconductor solutions for automotive, industrial, and IoT markets.

The CY8C54 family belongs to Infineon's PSoC® 5 platform, designed specifically for applications requiring deep integration of analog signal chains, real-time digital processing, and flexible firmware-defined peripherals in resource-constrained embedded systems.

FAQ

Does CY8C5468LTI-037 support USB device functionality without external components?

Yes. The part integrates a full-speed USB 2.0 physical layer (PHY) and requires only an external 24 MHz crystal, two 27 Ω series resistors on DP/DM lines, and standard USB termination. No external transceiver or level shifter is needed, and USB enumeration is handled entirely in firmware via the included USBFS component library in PSoC Creator™.

Can all 46 GPIOs be used simultaneously for analog input with the SAR ADCs?

No. While all GPIOs support analog routing, the dual SAR ADCs share a single analog bus and can sample only one channel at a time per ADC. With proper multiplexing via the AMUXBUS, up to 62 analog sources may be connected, but concurrent sampling is limited to two channels (one per ADC). Sequential scanning across multiple GPIOs is supported at up to 700 ksps aggregate rate.

What is the maximum update rate for the 8-bit VDACs, and how is output voltage range set?

The four 8-bit VDACs operate at up to 5.5 Msps with 1 µs settling time. Output voltage range is programmable from 0 to VDDA or 0 to 2×VDDA using internal gain stages; actual output swing is rail-to-rail (0 V to VDDA) when configured for unity gain, with ±10 mV offset error and 0.5% gain error over temperature.

Is the DFB capable of implementing custom filter coefficients at runtime?

Yes. The 24-bit DFB supports dynamic coefficient loading via DMA or CPU writes to its 64-word coefficient RAM. Filter coefficients can be updated on-the-fly during operation - for example, adapting FIR tap weights in response to changing acoustic noise profiles - without halting data flow or requiring CPU intervention for each sample.