Infineon Technologies CY8C5567LTI-079

Overview

CY8C5567LTI-079 from Infineon Technologies (acquired Cypress Semiconductor) is a 32-bit ARM Cortex-M3-based programmable system-on-chip (PSoC® 5) with 256 KB flash, 64 KB SRAM, 2-KB EEPROM, 67 MHz max CPU frequency, and integrated analog/digital peripherals including delta-sigma ADC (20-bit, 192 ksps), dual SAR ADCs (12-bit, 700 ksps), four opamps, four comparators, and USB 2.0 FS interface - deployed in industrial sensor hubs and embedded control systems.

For engineers reviewing the CY8C5567LTI-079 datasheet, CY8C5567LTI-079 pinout, CY8C5567LTI-079 application, or CY8C5567LTI-079 equivalent, key selection criteria include configurable UDB array count (24), analog routing flexibility across all GPIOs, CapSense® support, low-power hibernate mode (300 nA), and USB 2.0 FS compliance with external 24 MHz oscillator.

Technical Context

The CY8C5567LTI-079 implements a hierarchical mixed-signal architecture centered on an ARM Cortex-M3 core, supported by a programmable digital subsystem of 24 Universal Digital Blocks (UDBs) and a fully routable analog subsystem with shared bus access to all 60 GPIOs. Its clock tree integrates IMO (3–48 MHz), PLL (up to 67 MHz), 32.768 kHz RTC oscillator, and optional 4–25 MHz crystal input.

Analog signal chain capability includes simultaneous use of delta-sigma ADC (programmable gain ×0.25–×16, 8–20-bit resolution), two independent 12-bit SAR ADCs, four 8-bit DACs (5.5 Msps current or 1 Msps voltage), and four SC/CT blocks configurable as PGA, TIA, mixer, or sample-and-hold - all accessible via per-pin analog routing without dedicated analog pins.

Key Specifications

Pinout & Package

This device is packaged in a 68-pin QFN (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per the CY8C55 family pinout specification and support full analog/digital signal routing to all GPIOs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable mixed-signal SoC applications.

Compared with STM32F303VCT6 and MAX32660, CY8C5567LTI-079 uniquely combines delta-sigma ADC performance, full-GPIO analog routing, and UDB-based digital logic synthesis - enabling single-chip replacement of discrete analog signal chains and custom protocol engines.

Availability

CY8C5567LTI-079 is available at Aetrix Electronics and suitable for industrial sensor hubs, medical patient monitor front-ends, smart home touch interfaces, and automotive cabin control panels requiring stable component supply and long-term lifecycle support.

Supply support for CY8C5567LTI-079 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies acquired Cypress Semiconductor in 2020 and now owns the PSoC® portfolio. Infineon is a global semiconductor leader focused on power systems, automotive, and industrial applications.

The CY8C55 family belongs to Infineon's PSoC® 5 programmable SoC product line, designed to unify analog signal acquisition, digital processing, and system control in a single chip for rapidly evolving embedded applications.

FAQ

Does CY8C5567LTI-079 support USB device functionality without external components?

Yes. It integrates a full-speed USB 2.0 PHY and controller, requiring only an external 24 MHz crystal and standard USB termination resistors. No external transceiver or level shifter is needed, and USB enumeration is handled entirely in firmware using the provided USB Component library in PSoC Creator™.

Can all 60 GPIOs be used simultaneously for analog input with the delta-sigma ADC?

No. While all 60 GPIOs are routable to the analog subsystem, the delta-sigma ADC has one input channel with multiplexer support for up to 62 analog sources - meaning multiple GPIOs can be sequentially scanned, but only one is sampled at a time. Simultaneous sampling requires the two independent SAR ADCs, each with dedicated input channels.

What is the minimum supply voltage for hibernate mode operation?

The device supports hibernate mode down to 1.71 V on VDD, maintaining 300 nA current draw and full SRAM retention. This is enabled by an internal LDO regulator that remains active during hibernate, allowing operation from partially discharged batteries or energy-harvesting sources.

Is CapSense® functionality available on all GPIOs, including those with opamp outputs?

No. CapSense® is supported on all GPIOs except those configured as opamp outputs, as stated in the datasheet Note 1. Opamp output pins exhibit non-ideal capacitance characteristics that degrade touch sensitivity and SNR; designers must assign CapSense® electrodes to dedicated GPIOs without analog output routing.