Infineon Technologies CY8C5568LTI-114

Overview

CY8C5568LTI-114 from Infineon (acquired Cypress Semiconductor) is a programmable system-on-chip (PSoC® 5) integrating a 32-bit ARM Cortex-M3 CPU, 256 KB flash, 64 KB SRAM, 2-KB EEPROM, and configurable analog/digital peripherals including delta-sigma ADC (20-bit, 192 ksps), dual 12-bit SAR ADCs (700 ksps), four opamps, four comparators, and USB 2.0 FS interface - deployed in industrial sensor hubs and embedded control systems requiring mixed-signal reconfigurability.

For engineers reviewing the CY8C5568LTI-114 datasheet, CY8C5568LTI-114 pinout, CY8C5568LTI-114 application, or CY8C5568LTI-114 equivalent, key selection criteria include its 67 MHz CPU clock, 2.7–5.5 V operating range, 60 GPIO + 8 SIO + 2 USBIO routing flexibility, CapSense® support on any GPIO, and 300-nA hibernate mode with RAM retention.

Technical Context

The CY8C5568LTI-114 implements a hierarchical mixed-signal architecture centered on the ARM Cortex-M3 core, with dedicated analog and digital subsystems interconnected via configurable routing buses. Its analog subsystem includes a 1.024 V ±1% internal reference, programmable gain stage (×0.25 to ×16), and four SC/CT blocks supporting PGA, TIA, mixer, and sample-and-hold configurations.

Digital configurability is delivered through 24 universal digital blocks (UDBs), each combining PLD logic and state machines, enabling synthesis of custom peripherals like LIN 2.0, quadrature decoders, or CRC generators. The DFB supports 24-bit fixed-point FIR/IIR filtering at up to 67 MHz with 48-bit MAC per cycle, fed directly by ADC DMA without CPU overhead.

Key Specifications

Pinout & Package

Package: 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch), RoHS-compliant, industrial temperature grade (–40 °C to +85 °C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable mixed-signal SoC applications.

Compared with CY8C5568LTI-114, CY8C5868LTI-LP039 offers certified USB but sacrifices ultra-low-power hibernate, while STM32F303VCT6 provides stronger compute performance but demands external analog components and increases PCB area and BOM cost.

Availability

CY8C5568LTI-114 is available at Aetrix Electronics and suitable for industrial motor control, medical wearable sensor hubs, smart home touch interfaces, and programmable industrial PLC I/O modules requiring stable component supply across extended product lifecycles.

Supply support for CY8C5568LTI-114 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies acquired Cypress Semiconductor in 2020 and now owns the PSoC® portfolio, delivering scalable mixed-signal programmable SoCs for industrial, automotive, and IoT markets.

The CY8C55 family targets embedded systems demanding hardware-level analog/digital reconfigurability - designed to replace discrete signal chains and reduce design iteration time via firmware-defined peripheral allocation.

FAQ

Does CY8C5568LTI-114 support USB device enumeration without external crystal?

No. Full-Speed USB 2.0 operation requires a 24 MHz external crystal oscillator for precise 12 Mbps timing compliance. The internal IMO cannot meet USB frequency tolerance requirements. The crystal connects to XIN/XOUT pins, and USB functionality is disabled if the crystal is omitted or unstable.

Can all 60 GPIO pins be used simultaneously for analog input acquisition?

Yes - all 60 GPIO pins route to the analog bus and support delta-sigma or SAR ADC input. However, simultaneous sampling across all pins is limited by ADC throughput: the delta-sigma ADC achieves 192 ksps total, and each SAR ADC handles 700 ksps independently, so channel multiplexing is required for >4 analog inputs at full rate.

What is the maximum update rate for the 8-bit voltage DACs?

The four integrated voltage DACs (VDACs) support up to 1 Msps update rate with 8-bit resolution. Each VDAC output can be routed to any GPIO pin. For higher resolution, the UDB array can synthesize PWM-based DACs up to 10 bits at 48 kHz, using configurable timers and IDACs.

Is CapSense® functional on pins connected to opamp outputs?

No. The datasheet explicitly states that GPIOs with opamp outputs are not recommended for CapSense® use due to signal coupling and noise injection into the sensitive capacitance measurement circuitry. CapSense® should be assigned to dedicated GPIOs without analog output drivers enabled.