Infineon Technologies CY8C6137BZI-F34

Overview

CY8C6137BZI-F34 from Infineon is a dual-core PSOC™ 61 microcontroller featuring a 150-MHz Arm® Cortex®-M4F CPU and a dedicated 100-MHz Cortex®-M0+ for system management, 1-MB flash, 288-KB SRAM, integrated CAPSENSE™, USB full-speed device/host interface, and QSPI/XIP support - deployed in industrial IoT edge nodes requiring secure, low-power, sensor-fused operation.

For engineers reviewing the CY8C6137BZI-F34 datasheet, CY8C6137BZI-F34 pinout, CY8C6137BZI-F34 application, or CY8C6137BZI-F34 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip SIMO DC-DC (<1 µA quiescent), Deep Sleep current (7 µA with 64-KB SRAM retention), and hardware crypto acceleration for TLS/OTA firmware updates.

Technical Context

The CY8C6137BZI-F34 implements a tightly coupled dual-CPU subsystem where the Cortex-M4 executes application code while the Cortex-M0+ handles secure boot, interrupt routing, and peripheral arbitration - both cores share memory-mapped peripherals via a unified AXI bus. Clocking is managed through hierarchical sources: an 8-MHz IMO (±2%), 32-kHz ILO, external crystal oscillators (16–35 MHz & 32 kHz), and configurable PLL/FLL multipliers.

Its programmable analog subsystem includes a 12-bit 1-Msps SAR ADC with 16-channel sequencer and result averaging, two deep-sleep-capable comparators, a 12-bit DAC (<2-µs settling), and two opamps with low-power modes. The digital fabric integrates twelve UDBs (8 macrocells each), Smart I/O Boolean logic, and thirty-two TCPWM blocks supporting center-aligned PWM and comparator-triggered kill signals.

Key Specifications

Pinout & Package

CY8C6137BZI-F34 is housed in a 124-ball BGA package (8 mm × 8 mm, 0.5-mm pitch) with exposed thermal pad. Pin functions are organized into power domains (VDDIO, VDDD, VCCD, VBAT), clock inputs (XTAL_IN/OUT, IMO, ILO), dual-CPU debug (SWDIO/SWCLK), and programmable GPIO banks supporting Smart I/O Boolean operations during Deep Sleep.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6247BZI-D54 and STM32WB55RGV, CY8C6137BZI-F34 uniquely balances ultra-low-power dual-core execution, on-die programmable analog/digital logic, and field-proven CAPSENSE™ - making it optimal for resource-constrained, sensor-rich, and security-critical embedded designs where flexibility and power efficiency are co-primary constraints.

Availability

CY8C6137BZI-F34 is available at Aetrix Electronics and suitable for industrial IoT gateways, medical wearables, smart home hubs, and secure access terminals requiring stable component supply across multi-year production cycles.

Supply support for CY8C6137BZI-F34 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, and secure embedded solutions, with global manufacturing and R&D infrastructure.

The PSoC™ 6 family was designed specifically for secure, ultra-low-power IoT endpoints - integrating programmable analog/digital fabric, dual-CPU isolation, and hardware-rooted trust to simplify certification and reduce system-level BOM count.

FAQ

What is the maximum operating frequency of the Cortex-M4 core in CY8C6137BZI-F34?

The Arm Cortex-M4F core operates at up to 150 MHz with single-cycle multiply, floating-point unit, and memory protection unit enabled. This frequency is sustained under 1.1-V core supply; at 0.9 V, maximum frequency is reduced to maintain timing closure and power efficiency - verified in Infineon's characterization across temperature and voltage corners.

Does CY8C6137BZI-F34 support execute-in-place (XIP) from external flash?

Yes - the QSPI/SMIF interface supports XIP with on-the-fly AES-128 decryption and a dedicated 4-KB cache. External quad-SPI flash is mapped directly into the M4 instruction space, eliminating boot ROM copy overhead and reducing SRAM pressure during firmware execution.

Can the CAPSENSE™ subsystem operate during Deep Sleep mode?

Yes - CAPSENSE™ can run autonomously in Deep Sleep using the 32-kHz ILO clock and dedicated low-power sensing circuitry. It supports self- and mutual-capacitance scanning, automatic SmartSense tuning, and wake-on-touch event generation without waking either CPU core.

Is the USB interface limited to device-only operation?

No - the integrated USB full-speed PHY supports both device and host roles. Firmware-selectable configuration enables CDC, HID, or MSC class operation as a device, or enumeration of USB peripherals (e.g., keyboards, flash drives) as a host - all without external transceivers or level shifters.