Infineon Technologies CY8C6137FDI-F02T

Overview

CY8C6137FDI-F02T from Infineon is a dual-core PSOC™ 61 microcontroller featuring a 150-MHz Arm® Cortex®-M4F CPU and a dedicated 100-MHz Cortex®-M0+ for system functions, 1-MB flash, 288-KB SRAM, integrated CAPSENSE™, hardware cryptography accelerator, and QSPI/XIP support - deployed in IoT edge nodes requiring secure, low-power sensor fusion and wireless connectivity.

For engineers reviewing the CY8C6137FDI-F02T datasheet, CY8C6137FDI-F02T pinout, CY8C6137FDI-F02T application, or CY8C6137FDI-F02T equivalent, this device supports concurrent real-time control (M4), trusted boot & peripheral management (M0+), ultra-low-power Deep Sleep (7 µA with 64-KB retention), on-chip SIMO DC-DC converter (<1 µA quiescent), and programmable analog/digital blocks for rapid custom peripheral implementation.

Technical Context

The CY8C6137FDI-F02T implements a tightly coupled dual-CPU architecture where the M4 executes application firmware while the M0+ handles secure boot, power management, and inter-processor communication via IPC channels. Memory subsystem includes RWW flash with two 8-KB caches and 288-KB SRAM segmented into retention-capable banks.

Its clocking system integrates an 8-MHz IMO (±2%), 32-kHz ILO, PLL/FLL frequency multipliers, and integer/fractional peripheral dividers - enabling precise timing control across TCPWM, SCB, USB, and SMIF peripherals. The device uses a 124-BGA package with 100 GPIOs, including six overvoltage-tolerant pins and two Smart I/O ports supporting Boolean logic in Deep Sleep.

Key Specifications

Pinout & Package

The CY8C6137FDI-F02T is housed in a 124-ball BGA package (8 mm × 8 mm, 0.5-mm pitch) with exposed thermal pad. Pin assignment follows Infineon's standard PSOC™ 61 124-BGA layout, supporting full GPIO, analog, power, clock, and debug interface routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6137FDI-F02T, CY8C6247FDI-D43T offers integrated BLE at the expense of flash and analog resources, while STM32WB55RGV provides lower-cost wireless integration but lacks hardware-enforced security partitioning and programmable analog/digital blocks essential for differentiated HMI and sensor processing.

Availability

CY8C6137FDI-F02T is available at Aetrix Electronics and suitable for wearable health monitors, smart home sensor hubs, industrial predictive maintenance nodes, and secure access control terminals requiring stable component supply, long-term lifecycle assurance, and qualified automotive-grade packaging.

Supply support for CY8C6137FDI-F02T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and secure embedded solutions, with global R&D centers and ISO/TS 16949-certified manufacturing.

The PSOC™ 6 product line targets secure, ultra-low-power IoT endpoints - combining Arm dual-core processing, programmable analog/digital fabric, and hardware-rooted security to accelerate development of certified edge devices.

FAQ

Does CY8C6137FDI-F02T support USB device and host modes simultaneously?

No. The device integrates a single USB Full-Speed interface that operates in either device or host mode, selected at runtime via firmware configuration. Simultaneous dual-role operation is not supported; external USB switch ICs or multiplexers are required for dynamic role switching in field-deployed systems.

What is the maximum operating frequency of the QSPI interface in octal mode?

The QSPI interface supports octal mode at up to 80 MHz clock frequency, achieving 640 Mbps effective throughput (8 bits × 80 MHz). This is confirmed in the "Serial Memory Interface (SMIF)" section of the datasheet (Rev. *R, Table 6-13), and requires proper PCB layout with matched trace lengths and controlled impedance.

Can the Cortex-M0+ core be used for application code execution?

No. Per Infineon's documentation, the Cortex-M0+ in PSOC™ 61 devices is reserved exclusively for system-level functions including secure boot, power management, and inter-processor communication. Application firmware must run solely on the Cortex-M4F core; the M0+ is not accessible to user code.

Is the 124-BGA package of CY8C6137FDI-F02T compatible with reflow soldering per J-STD-020?

Yes. The 124-BGA package complies with JEDEC J-STD-020D moisture sensitivity level (MSL) 3 and supports standard Pb-free reflow profiles (peak temperature 260°C, time above liquidus 60–90 seconds). Bake requirements and floor life are specified in Infineon's packaging documentation (Document No. 002-21414, Section 5.1).