Infineon Technologies CY8C6144AZQ-S4F92

Overview

CY8C6144AZQ-S4F92 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller with 256 KB flash, 128 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography acceleration-designed for secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion and wireless coexistence.

For engineers reviewing the CY8C6144AZQ-S4F92 datasheet, CY8C6144AZQ-S4F92 pinout, CY8C6144AZQ-S4F92 application, or CY8C6144AZQ-S4F92 equivalent, this MCU delivers verified Deep Sleep current of 7 µA with 64 KB SRAM retention, dual 12-bit SAR ADCs (2 Msps), and programmable analog/digital subsystems enabling rapid customization of mixed-signal control paths without external components.

Technical Context

The device implements a tightly coupled dual-CPU architecture: the 150-MHz Cortex-M4F handles application processing and floating-point math, while the 100-MHz Cortex-M0+ manages system-level tasks including security boot, power sequencing, and peripheral arbitration-both cores operate at user-selectable 1.1 V or 0.9 V supply rails.

Its programmable analog subsystem includes two synchronized 12-bit SAR ADCs with 16-channel sequencer and result averaging, one 12-bit DAC (<2 µs settling), two low-power comparators active in Deep Sleep, and two opamps with continuous-time operation-enabling closed-loop sensing and actuation without waking the main CPU.

Key Specifications

Pinout & Package

This device is packaged in an 80-pin TQFP (12 mm × 12 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per Infineon's official CY8C61x4 Datasheet Rev. *H, Section 4 "Pinouts".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with LPC55S69 and RA6M5, CY8C6144AZQ-S4F92 uniquely combines CAN FD, USB FS, dual SAR ADCs, and CAPSENSE™ in a single die-reducing BOM count by up to 7 components and enabling sub-10 µA system-level sleep states without external supervisors.

Availability

CY8C6144AZQ-S4F92 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home gateways, medical wearables, and automotive body controllers requiring stable component supply across multi-year production cycles.

Supply support for CY8C6144AZQ-S4F92 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, sensing, and secure microcontrollers for industrial, automotive, and IoT markets.

This part belongs to the PSoC™ 61 product line-engineered specifically for secure, ultra-low-power edge intelligence with integrated analog/digital programmability and hardware-enforced trust anchors.

FAQ

Does CY8C6144AZQ-S4F92 support JTAG debugging?

Yes-it features a standard SWD/SWJ interface compatible with industry tools including Segger J-Link and Infineon's KitProg3. The 32-bit Silicon ID is accessible via SWJ, with MSB encoding die revision and LSBs containing manufacturer ID "069" in hex. Debug access can be permanently disabled via eFuse for production security.

What is the maximum operating frequency of the internal PLL?

The on-chip PLL supports output frequencies up to 150 MHz when driven by the 8-MHz IMO or external crystal sources. It achieves ±50 ppm stability over temperature and voltage when locked to a 32-kHz reference, meeting timing requirements for USB packet framing and CAN FD bit timing without external clock sources.

Can the Smart I/O block operate independently during Deep Sleep?

Yes-the Smart I/O port (6 pins) retains full Boolean logic functionality-including AND/OR/XOR and state retention-while the entire system resides in System Deep Sleep mode. This enables autonomous wake-up triggers from GPIO transitions or analog comparator outputs without CPU intervention or increased current draw.

Is the 12-bit DAC rail-to-rail and what is its output impedance?

The integrated 12-bit voltage-mode DAC provides rail-to-rail output swing (VSSA to VDDA) with a typical output impedance of 200 Ω. Its <2 µs settling time allows direct driving of low-bandwidth analog actuators like piezo buzzers or LED bias circuits without external buffering in most designs.