Infineon Technologies CY8C6144LQI-S4F12
- Part No.:
- CY8C6144LQI-S4F12
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
CY8C6144LQI-S4F12.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 68QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,330
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CY8C6144LQI-S4F12 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller with 256-KB flash, 128-KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography acceleration-designed for secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion and wireless coexistence.
For engineers reviewing the CY8C6144LQI-S4F12 datasheet, CY8C6144LQI-S4F12 pinout, CY8C6144LQI-S4F12 application, or CY8C6144LQI-S4F12 equivalent, this device supports concurrent BLE/Wi-Fi coexistence via Smart I/O and Deep Sleep SCB, delivers 7 µA Deep Sleep current with 64-KB SRAM retention, and integrates on-chip DC-DC buck converter with <1-µA quiescent current for battery-powered industrial sensing.
Technical Context
The CY8C6144LQI-S4F12 implements a tightly coupled dual-CPU architecture where the Cortex-M4F (150 MHz) handles application processing and signal analysis while the Cortex-M0+ (100 MHz) is reserved exclusively for system-level functions including security boot, power management, and peripheral arbitration-enabling deterministic real-time response without software contention.
Its programmable analog subsystem includes two synchronized 12-bit 2-Msps SAR ADCs with 16-channel sequencer and result averaging, one 12-bit DAC (<2-μs settling), two low-power comparators operational in Deep Sleep mode, and a built-in temperature sensor directly connected to ADC-supporting closed-loop thermal compensation and battery monitoring at sub-µA system current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F with FPU + 100-MHz Cortex-M0+ (system-only, not user-accessible) |
| Memory | 256-KB application flash (RWW), 32-KB supervisory flash, 128-KB SRAM with programmable retention granularity |
| Power Consumption | 7 µA in Deep Sleep with 64-KB SRAM retention; on-chip DC-DC buck converter with <1-µA quiescent current |
| Analog Peripherals | Two 12-bit 2-Msps SAR ADCs (synchronized sampling, 16-channel sequencer), one 12-bit DAC (<2-μs settling), two Deep Sleep-capable comparators |
| Communication | One CAN FD block, six configurable SCBs (five runtime-configurable as SPI/I²C/UART, one Deep Sleep SCB as SPI/I²C), USB Full-Speed device interface |
| Security | Hardware crypto accelerators (AES, ECC, SHA), TRNG, authentication during boot using hardware hashing, up to eight protection contexts |
| Package | 80-pin TQFP (12 × 12 mm, 0.5-mm pitch), RoHS-compliant, lead-free |
Pinout & Package
Package: 80-pin Thin Quad Flat Package (TQFP), 12 mm × 12 mm body, 0.5 mm pitch, exposed thermal pad (EPAD) on underside for enhanced thermal dissipation in high-duty-cycle applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO0–VDDIO5 | I/O Power Supply Rails | Independent 1.7–3.6 V supply domains per port group enable mixed-voltage interfacing (e.g., 1.8-V sensors + 3.3-V radios) |
| P0[0]–P0[7], P1[0]–P1[7], etc. | Programmable GPIOs (up to 62 total) | Configurable drive modes, slew rates, and strengths; two pins support overvoltage tolerance (OVT) up to 5.5 V |
| SWDCLK / SWDIO | Serial Wire Debug Interface | Two-pin debug interface supporting programming, real-time trace, and secure debug disable via eFuse configuration |
| USB_DP / USB_DM | USB Full-Speed Differential Pair | Integrated transceiver compliant with USB 2.0 Full-Speed (12 Mbps); no external PHY required |
| CAN_TX / CAN_RX | CAN FD Physical Layer Interface | Dedicated differential pair supporting CAN FD up to 5 Mbps; internal termination and filtering reduce BOM count |
| VREFH / VREFL | Analog Reference Inputs | External reference inputs for SAR ADC and DAC; support ratiometric measurements and precision sensor biasing |
Key Features
| Feature | Design Value |
|---|---|
| Smart I/O Subsystem | 6-pin Boolean logic engine enabling stateless GPIO preprocessing (AND/OR/XOR) during System Deep Sleep-reducing wake-up latency for motion-triggered wake events |
| Capacitive Sensing (CSD) | Capacitive Sigma-Delta engine with SmartSense auto-tuning, liquid-tolerant operation, and dynamic self/mutual sensing-enabling waterproof touch interfaces in consumer appliances |
| Segment LCD Driver | Supports up to 61 segments × 8 commons with direct Deep Sleep operation-eliminates need for external display controllers in battery-powered meters |
| Quad-SPI (SMIF) | Execute-In-Place (XIP) from external flash with on-the-fly AES-128 encryption, 4-KB cache, and 320 Mbps throughput-secures firmware updates and reduces code footprint in resource-constrained edge devices |
| Deep Sleep SCB | Single SCB retaining SPI/I²C functionality in Deep Sleep mode-enables continuous sensor polling (e.g., environmental monitors) without CPU wake-up |
Applications
| Industrial Wireless Sensor Node | Secure Smart Metering |
|---|---|
|
Use Scenario: Battery-powered vibration and temperature monitor deployed in remote pump stations with 10-year lifespan requirement. IC Role / Device Role / Timing Role: Dual-core MCU performs FFT-based anomaly detection (M4F) while M0+ manages secure OTA updates, clock calibration, and watchdog supervision. Use Value: 7 µA Deep Sleep current with 64-KB SRAM retention enables >10-year operation on CR123A; integrated CAN FD allows local fieldbus integration without gateway. |
Use Scenario: UL-certified electricity meter with tamper detection, encrypted billing data, and HPLC communication. IC Role / Device Role / Timing Role: Hardware crypto accelerator performs AES-128 encryption of consumption logs; TRNG seeds secure key generation; RTC maintains billing timestamp integrity. Use Value: On-chip eFuse array stores unique device keys; certified bootloader prevents unauthorized firmware execution-meeting IEC 62056 and ANSI C12.22 requirements. |
| Medical Wearable Hub | Home Appliance Control Panel |
|
Use Scenario: ECG/PPG wearable aggregating biometric data and transmitting via BLE to smartphone. IC Role / Device Role / Timing Role: SAR ADCs acquire synchronized analog front-end signals; Smart I/O filters motion artifacts before M4F processing; Deep Sleep SCB handles BLE event scheduling. Use Value: Two synchronized 2-Msps ADCs eliminate inter-channel skew; integrated temperature sensor enables real-time gain calibration-improving SNR by ≥12 dB over ambient range. |
Use Scenario: Touch-enabled oven control panel with segment LCD display, capacitive knobs, and motor drivers. IC Role / Device Role / Timing Role: CSD subsystem detects wet-finger and proximity gestures; Segment LCD driver powers display in Deep Sleep; TCPWMs generate precise PWM for fan speed control. Use Value: SmartSense auto-tuning eliminates factory calibration; 61-segment LCD driver replaces external display controller-reducing BOM cost by $0.32/unit at 100k volume. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP LPC55S69 | Single Cortex-M33 core (no M0+ companion); lacks integrated CAN FD and SMIF; includes NPU for ML inference | Better suited for AI-at-edge inference workloads; requires external CAN transceiver and flash memory controller | Select when neural network acceleration outweighs CAN FD integration and ultra-low-power Deep Sleep requirements |
| Renesas RA6M5 | Single Cortex-M33 core; includes Ethernet MAC but no CAN FD; higher active power (120 µA/MHz vs CY8C6144's 45 µA/MHz) | Preferred for industrial gateways needing wired connectivity; lacks Smart I/O and CSD subsystems | Choose when Ethernet + USB host capability is mandatory and Deep Sleep current >15 µA is acceptable |
Compared with LPC55S69 and RA6M5, CY8C6144LQI-S4F12 uniquely combines CAN FD, SMIF with XIP encryption, and sub-µA Deep Sleep SCB-making it optimal for battery-powered, fieldbus-connected IoT endpoints where firmware security and multi-sensor concurrency are critical.
Availability
CY8C6144LQI-S4F12 is available at Aetrix Electronics and suitable for industrial wireless sensor nodes, secure smart metering systems, medical wearables, and home appliance control panels requiring stable component supply across long product lifecycles.
Supply support for CY8C6144LQI-S4F12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers-with global R&D centers and ISO/TS 16949-certified wafer fabs.
CY8C6144LQI-S4F12 belongs to the PSoC™ 61 MCU product line, engineered specifically for secure, ultra-low-power IoT edge devices that demand concurrent wireless connectivity, sensor fusion, and hardware-enforced trust anchors.
FAQ
Does CY8C6144LQI-S4F12 support JTAG debugging?
No-CY8C6144LQI-S4F12 uses Serial Wire Debug (SWD) only. It features SWDCLK and SWDIO pins compatible with standard ARM debug probes (e.g., Segger J-Link, ST-Link v3). JTAG is not implemented; the SWJ-DP interface supports full debug, trace, and secure programming capabilities including eFuse configuration and flash encryption key provisioning.
What is the maximum operating frequency of the internal PLL?
The internal PLL supports output frequencies up to 150 MHz, derived from the 8-MHz IMO or external crystal sources. It achieves ±50 ppm stability over temperature and voltage when locked to a 32-kHz crystal reference, enabling precise timing for USB Full-Speed and CAN FD bit-rate generation without external clock components.
Can the Cortex-M0+ core be used for application code?
No-the Cortex-M0+ core in CY8C6144LQI-S4F12 is reserved exclusively for system-level firmware (bootloader, power management, security services) and is not accessible to user applications. All application code must run on the Cortex-M4F core; the M0+ operates transparently under the PSoC™ 6 firmware abstraction layer.
Is the on-chip DC-DC buck converter mandatory for operation?
No-the DC-DC buck converter is optional and can be bypassed to use linear regulators (LDOs) for VCC and VDDD. When enabled, it supplies VDDD from VBUS (4.5–5.5 V) with >90% efficiency and <1-µA quiescent current; when disabled, the device operates from 1.7–3.6 V via external LDOs or direct battery connection to VDDD/VCC rails.
CY8C6144LQI-S4F12 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4F
- Core Size:
- 32-Bit
- Speed:
- 150MHz
- Connectivity:
- FIFO, I2C, IrDA, LINbus, Microwire, SmartCard, SPI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, CapSense, DMA, LCD, LVD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 16x12b Sigma-Delta; D/A 2x7b, 1x8/12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6144LQI-S4F12 FAQ
1.How can I place an order for CY8C6144LQI-S4F12 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6144LQI-S4F12 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6144LQI-S4F12 reliable?
The price and inventory of CY8C6144LQI-S4F12 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6144LQI-S4F12 is usually 5 days.
3.What payment methods are accepted for CY8C6144LQI-S4F12?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6144LQI-S4F12 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6144LQI-S4F12?
CY8C6144LQI-S4F12 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6144LQI-S4F12 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6144LQI-S4F12?
For technical support, including CY8C6144LQI-S4F12 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6144LQI-S4F12 requirements.
6.How does Aetrix verify that CY8C6144LQI-S4F12 is sourced from the original manufacturer or authorized distributors?
All CY8C6144LQI-S4F12 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6144LQI-S4F12 meets industry standards.
7.What is the process for return or replacement of CY8C6144LQI-S4F12?
All CY8C6144LQI-S4F12 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6144LQI-S4F12, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6144LQI-S4F12 part is unused and in its original packaging.
Return procedure for CY8C6144LQI-S4F12:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CY8C6144LQI-S4F12 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…
Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…
A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…
Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…
Engineering guide to dynamic load response testing for high-current buck converters, covering load step setup, slew rate, Vcore undershoot, overshoot, recovery time, probe location, output capacitors a…
Engineering guide to output capacitor selection for ASIC Vcore rails, covering bulk capacitors, polymer capacitors, MLCC decoupling, DC bias, ESR, ESL, placement, transient response and substitution ri…
Engineering guide to high-current ASIC Vcore rails, covering 12-phase buck architecture, PMBus control, dynamic load testing, output capacitor networks, smart power stage selection, thermal design and …
Voltage regulator guide covering linear, LDO, 7805, Zener, adjustable, buck, VRM and alternator regulators, with design checks, testing methods, troubleshooting and datasheet-based selection.
Amplifier guide covering voltage, current and power amplification, gain, feedback, amplifier classes, audio and RF applications, op-amp circuits, transimpedance amplifiers, datasheet selection and trou…

