Infineon Technologies CY8C6144LQI-S4F62

Overview

CY8C6144LQI-S4F62 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller with 256-KB flash, 128-KB SRAM, integrated CAN FD, USB Full-Speed, and programmable analog/digital subsystems - designed for secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion, capacitive touch, and wireless coexistence.

For engineers reviewing the CY8C6144LQI-S4F62 datasheet, CY8C6144LQI-S4F62 pinout, CY8C6144LQI-S4F62 application, or CY8C6144LQI-S4F62 equivalent, this device supports concurrent firmware isolation (CM4 for application, CM0+ for system services), Deep Sleep mode at 7 µA with 64-KB SRAM retention, hardware crypto acceleration, and SmartSense™ capacitive sensing - critical for battery-powered industrial sensors and smart home controllers.

Technical Context

The CY8C6144LQI-S4F62 implements a tightly coupled dual-CPU architecture where the 150-MHz Cortex-M4F executes application code with FPU and MPU, while the 100-MHz Cortex-M0+ handles boot, security, and power management - with IPC and shared memory enabling deterministic inter-core communication. Its clock system integrates IMO (8 MHz ±2%), ILO (32 kHz), PLL/FLL, and crystal oscillators (16–35 MHz & 32 kHz) to support dynamic frequency scaling across six power modes.

Peripherals are partitioned for low-power operation: one Deep Sleep-capable SCB (SPI/I²C), two SAR ADCs (12-bit, 2-Msps, synchronized sampling), a dedicated CAN FD controller, and Smart I/O (6 pins) enabling Boolean logic in System Deep Sleep. The SMIF interface supports XIP from external Quad-SPI Flash with on-the-fly AES encryption and 4-KB cache.

Key Specifications

Pinout & Package

Package: 80-pin TQFP (12 mm × 12 mm, 0.5 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with STM32WB55RGV6 and RA6M5G32CBM#AC0, the CY8C6144LQI-S4F62 uniquely integrates CAN FD, SmartSense™ capacitive sensing, and programmable Smart I/O - reducing BOM count and enabling autonomous low-power operation without external assist chips.

Availability

CY8C6144LQI-S4F62 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home hubs, medical wearables, and automotive body controllers requiring stable component supply, long-term lifecycle support, and qualified automotive-grade variants.

Supply support for CY8C6144LQI-S4F62 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, security solutions, and embedded controllers - with leadership in radar, MEMS, and industrial power semiconductors.

The PSOC™ 6 product line targets secure, ultra-low-power IoT endpoints, combining programmable analog/digital fabric with Arm dual-core MCUs to eliminate external components in sensor, touch, and connectivity applications.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6144LQI-S4F62?

The Cortex-M4F core operates at up to 150 MHz, with single-cycle multiply and integrated floating-point unit (FPU). This frequency is achievable under full VDDD supply (1.1 V) and ambient temperatures ≤85°C, as validated in the device's electrical specifications table (Section 6.2.2 of datasheet 002-33480 Rev. *H).

Does CY8C6144LQI-S4F62 support hardware-based secure boot with public-key verification?

Yes - it authenticates firmware during boot using hardware-accelerated SHA-256 hashing of the image header and signature. Public-key verification is implemented via ROM-based boot code that validates ECDSA signatures against keys stored in OTP eFuse, ensuring immutable root-of-trust.

Can the Smart I/O block operate independently while the main CPU cores are in Deep Sleep mode?

Yes - the Smart I/O port (6 pins) remains fully functional in System Deep Sleep mode, executing Boolean logic (AND/OR/XOR) on GPIO inputs and generating wake-up events without CPU intervention. Its configuration is retained in dedicated low-power registers.

Is the CAN FD peripheral compliant with ISO 11898-1:2015 and capable of bit rates above 1 Mbps?

Yes - the integrated CAN FD controller complies with ISO 11898-1:2015 and supports data bit rates up to 5 Mbps in FD mode. It includes programmable bit timing, error counters, and message RAM with hardware acceptance filtering - verified in the functional description section (3.5.4) and electrical specs (Table 6-43).