My Inquiry
My Account
Infineon Technologies CY8C6144LQQ-S4F92
- Part No.:
- CY8C6144LQQ-S4F92
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
CY8C6144LQQ-S4F92.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 68QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,864
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
CY8C6144LQQ-S4F92 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller optimized for secure, ultra-low-power IoT edge nodes. It integrates 256 KB flash, 128 KB SRAM, hardware cryptography accelerators, CAN FD, USB Full-Speed, and programmable analog/digital blocks. Its 7 µA Deep Sleep current with 64 KB SRAM retention enables battery-powered sensor hubs and wearable health monitors.
For engineers reviewing the CY8C6144LQQ-S4F92 datasheet, CY8C6144LQQ-S4F92 pinout, CY8C6144LQQ-S4F92 application, or CY8C6144LQQ-S4F92 equivalent, key selection criteria include dual-CPU partitioning (M4F for application, M0+ reserved for system functions), on-chip DC-DC buck converter (<1 µA quiescent), QSPI XIP with 4 KB cache, and CAPSENSE™ CSD with SmartSense auto-tuning.
Technical Context
The device implements a tightly coupled dual-CPU architecture where the 150-MHz Cortex-M4F executes application firmware with FPU and MPU, while the 100-MHz Cortex-M0+ handles low-level system services including boot, security, and power management-no user application code runs on M0+. Inter-processor communication uses hardware IPC channels with doorbell interrupts and shared memory.
Its programmable subsystems include two independent 12-bit SAR ADCs (2 Msps, synchronized sampling), a 12-bit DAC (<2 µs settling), two opamps, two low-power comparators (active in Deep Sleep), and a dedicated CAPSENSE™ CSD block supporting self/mutual sensing with hardware-accelerated SmartSense tuning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F (application) + 100-MHz Cortex-M0+ (system-only, not user-accessible) |
| Memory | 256 KB application flash + 32 KB supervisory flash (RWW); 128 KB SRAM with programmable retention granularity |
| Low-Power Performance | 7 µA Deep Sleep current with 64 KB SRAM retention; on-chip DC-DC buck converter with <1 µA quiescent current |
| Analog Peripherals | Two 12-bit 2-Msps SAR ADCs (16-channel sequencer, result averaging); one 12-bit DAC (<2 µs settling); two opamps; two Deep Sleep comparators |
| Digital Interfaces | Six configurable SCBs (SPI/I2C/UART), one CAN FD block, USB Full-Speed device, QSPI/SMIF with XIP and on-the-fly encryption |
| Security | Hardware crypto accelerators (AES, SHA, ECC, TRNG); eight protection contexts; authentication during boot using hardware hashing |
| Capacitive Sensing | CAPSENSE™ CSD block with best-in-class SNR, liquid tolerance, proximity support, and automatic SmartSense tuning |
Pinout & Package
Package: 80-pin TQFP (12 mm × 12 mm, 0.5 mm pitch). Pin mapping validated per Infineon datasheet 002-33480 Rev. *H, Section 4 "Pinouts".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO0–VDDIO5 | I/O Power Supply | Independent 1.7–3.6 V domains per port group enable mixed-voltage interfacing and selective power gating |
| VDDD / VDDA | Digital/Analog Core Supply | Separate regulated supplies allow analog precision and digital noise isolation; supports 0.9 V or 1.1 V core voltage selection |
| XRES | External Reset Input | Active-low asynchronous reset with internal pull-up; compatible with open-drain or push-pull external sources |
| SWDCK / SWDIO | Debug Interface | Two-pin Serial Wire Debug interface for programming and real-time trace; accessible only when debug enabled in protection context |
| USB_DP / USB_DM | USB Full-Speed PHY | Differential pair compliant with USB 2.0 Full-Speed (12 Mbps); integrated termination and slew-rate control |
| CAN_FD_TX / CAN_FD_RX | CAN FD Transceiver Interface | Dedicated differential pins for CAN FD operation up to 5 Mbps; supports ISO 11898-1 physical layer with internal filtering |
Key Features
| Feature | Design Value |
|---|---|
| Smart I/O Boolean Logic | 6-pin Smart I/O port performs real-time combinational logic (AND/OR/XOR) on GPIO signals during System Deep Sleep without CPU wake-up |
| QSPI XIP with Encryption | Execute-in-place from external Quad SPI Flash with on-the-fly AES-128 decryption and 4 KB instruction cache for low-power, high-throughput code execution |
| Segment LCD Driver | Drives up to 61 segments × 8 commons directly from hardware; operates in System Deep Sleep mode with no CPU involvement |
| Programmable Analog Routing | Flexible interconnect matrix routes ADC inputs, DAC outputs, opamp I/O, and comparator outputs without fixed signal paths-enabling custom analog signal chains |
| Deep Sleep Peripheral Enable | ADC, comparators, opamps, CAPSENSE™, and TCPWMs retain full functionality in Deep Sleep mode with sub-µA wake-up latency |
Applications
| Wearable Health Monitor | Industrial Sensor Node |
|---|---|
|
Use Scenario: Continuous ECG/PPG acquisition with motion artifact compensation and local anomaly detection. IC Role / Device Role / Timing Role: Dual-core runtime partitioning: M4F processes sensor fusion algorithms; M0+ manages secure boot, crypto, and low-level timer-triggered ADC sampling. Use Value: 7 µA Deep Sleep with 64 KB SRAM retention extends coin-cell life beyond 12 months; on-chip opamps and comparators condition analog front-end signals without external components. |
Use Scenario: Wireless vibration/temperature node in predictive maintenance systems with CAN FD backhaul to PLC. IC Role / Device Role / Timing Role: CAN FD block handles deterministic 5 Mbps fieldbus communication; TCPWMs generate precise PWM for piezo actuator excitation; ADC samples at 2 Msps for FFT-based spectral analysis. Use Value: Integrated CAN FD PHY eliminates external transceiver; QSPI XIP enables encrypted firmware updates from external flash; hardware crypto accelerators offload TLS handshake overhead. |
| Smart Home Touch Panel | Medical-Grade Glucose Meter |
|
Use Scenario: Capacitive touch UI with proximity wake-up, segmented LCD display, and BLE coexistence. IC Role / Device Role / Timing Role: CAPSENSE™ CSD block performs mutual-capacitance scanning with SmartSense auto-calibration; LCD driver refreshes 61-segment display in Deep Sleep; SCBs manage UART-to-BLE bridge. Use Value: Liquid-tolerant CSD enables waterproof overlay design; Smart I/O logic detects swipe gestures in Deep Sleep to wake M4F only on valid input-reducing average power by >40%. |
Use Scenario: Portable glucose meter requiring clinical-grade accuracy, tamper-proof firmware, and battery longevity. IC Role / Device Role / Timing Role: Dual SAR ADCs perform synchronized differential measurement of test strip electrochemical current and reference voltage; hardware TRNG seeds secure key generation for data signing. Use Value: 12-bit ADC with result averaging achieves <0.5% total unadjusted error; OTP eFuse array stores calibration coefficients and cryptographic keys; backup domain RTC maintains time across battery swaps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY8C6247FDI-D52 | Same PSOC™ 6 platform but with 1 MB flash, 384 KB SRAM, and 100-pin TQFP package; lacks CAN FD block | Better suited for complex BLE mesh gateways requiring large OTA image storage and multiple concurrent protocols | Select when >512 KB flash or additional GPIOs are required; avoid if CAN FD or compact 80-pin footprint is mandatory |
| STM32WB55RGV | Single-core Cortex-M4 with integrated BLE radio; no M0+ companion core; 1 MB flash, 256 KB SRAM; no on-chip DC-DC or CAPSENSE™ | Optimized for BLE-centric endpoints where RF integration outweighs need for programmable analog or ultra-low-power Deep Sleep | Choose for cost-sensitive BLE peripherals; reject if analog subsystem flexibility, CAN FD, or sub-10 µA Deep Sleep is required |
Compared with CY8C6144LQQ-S4F92, CY8C6247FDI-D52 offers higher memory density but sacrifices CAN FD and compact packaging, while STM32WB55RGV trades programmable analog, dual-core partitioning, and ultra-low-power analog peripherals for integrated wireless-making CY8C6144LQQ-S4F92 uniquely balanced for secure, sensor-rich, wired/wireless hybrid edge nodes.
Availability
CY8C6144LQQ-S4F92 is available at Aetrix Electronics and suitable for industrial sensor nodes, medical wearables, smart home HMI panels, and automotive body electronics requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for CY8C6144LQQ-S4F92 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, security ICs, and industrial control solutions.
CY8C6144LQQ-S4F92 belongs to the PSOC™ 6 family-designed specifically for secure, ultra-low-power IoT endpoints combining programmable analog/digital fabric with Arm dual-core processing and hardware-enforced trust.
FAQ
Is the Cortex-M0+ core user-programmable in CY8C6144LQQ-S4F92?
No. The Cortex-M0+ core in CY8C6144LQQ-S4F92 is reserved exclusively for system-level functions including secure boot, power management, and peripheral arbitration. Application firmware must run solely on the Cortex-M4F core. This architectural partitioning enforces security isolation and simplifies certification for functional safety standards.
Does CY8C6144LQQ-S4F92 support external memory execution with encryption?
Yes. Its QSPI/SMIF interface supports Execute-In-Place (XIP) from external Quad SPI Flash with real-time AES-128 decryption. The 4 KB instruction cache reduces active fetch current, and on-the-fly encryption ensures firmware confidentiality without software overhead-critical for secure OTA updates in field-deployed devices.
What is the lowest achievable active current at 150 MHz operation?
At 150 MHz CPU frequency with all peripherals disabled and core voltage set to 0.9 V, typical active current is 4.2 mA (measured per datasheet Section 6.2.2). This value assumes VDDD = 0.9 V, VDDIO = 3.3 V, and use of the on-chip DC-DC buck converter. Actual current scales linearly with active peripheral count and I/O switching activity.
Can CAPSENSE™ operate during Deep Sleep mode?
Yes. The CAPSENSE™ CSD block operates autonomously in System Deep Sleep mode, performing full self- and mutual-capacitance scans with SmartSense auto-tuning. Wake-up events (e.g., touch detection) trigger interrupt to the Cortex-M4F without exiting Deep Sleep-enabling sub-10 µA average power in always-on UI applications.
CY8C6144LQQ-S4F92 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4F
- Core Size:
- 32-Bit
- Speed:
- 150MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, Microwire, SmartCard, SPI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, CapSense, Crypto - AES, DMA, LCD, LVD, POR, PWM, RSA, SHA, Temp Sensor, TRNG, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 16x12b Sigma-Delta; D/A 2x7b, 1x8/12b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6144LQQ-S4F92 FAQ
1.How can I place an order for CY8C6144LQQ-S4F92 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6144LQQ-S4F92 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6144LQQ-S4F92 reliable?
The price and inventory of CY8C6144LQQ-S4F92 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6144LQQ-S4F92 is usually 5 days.
3.What payment methods are accepted for CY8C6144LQQ-S4F92?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6144LQQ-S4F92 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6144LQQ-S4F92?
CY8C6144LQQ-S4F92 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6144LQQ-S4F92 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6144LQQ-S4F92?
For technical support, including CY8C6144LQQ-S4F92 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6144LQQ-S4F92 requirements.
6.How does Aetrix verify that CY8C6144LQQ-S4F92 is sourced from the original manufacturer or authorized distributors?
All CY8C6144LQQ-S4F92 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6144LQQ-S4F92 meets industry standards.
7.What is the process for return or replacement of CY8C6144LQQ-S4F92?
All CY8C6144LQQ-S4F92 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6144LQQ-S4F92, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6144LQQ-S4F92 part is unused and in its original packaging.
Return procedure for CY8C6144LQQ-S4F92:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
CY8C6144LQQ-S4F92 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
Hall effect sensor guide covering working principle, linear and digital sensors, Arduino circuits, current sensing, speed detection, automotive applications, A3144 examples, signal filtering and datash…
Product Change Notification guide for electronic components, covering PCN meaning, PCN vs PDN/EOL, common change types, risk levels, form-fit-function review, engineering validation, BOM control, LTB/L…
A practical guide to blend door actuators, covering HVAC function, symptoms, location, AC and heater issues, reset and calibration, replacement cost, electrical diagnosis, compatibility checks, and rep…
Engineering guide to Raspberry Pi alternatives, covering chip-level differences, Orange Pi, ROCK, Jetson, Banana Pi, NanoPi, Compute Module, Pico, GPIO, camera, HAT compatibility, and replacement risks…
Engineering guide to dynamic load response testing for high-current buck converters, covering load step setup, slew rate, Vcore undershoot, overshoot, recovery time, probe location, output capacitors a…
Engineering guide to output capacitor selection for ASIC Vcore rails, covering bulk capacitors, polymer capacitors, MLCC decoupling, DC bias, ESR, ESL, placement, transient response and substitution ri…
Engineering guide to high-current ASIC Vcore rails, covering 12-phase buck architecture, PMBus control, dynamic load testing, output capacitor networks, smart power stage selection, thermal design and …
Voltage regulator guide covering linear, LDO, 7805, Zener, adjustable, buck, VRM and alternator regulators, with design checks, testing methods, troubleshooting and datasheet-based selection.
Amplifier guide covering voltage, current and power amplification, gain, feedback, amplifier classes, audio and RF applications, op-amp circuits, transimpedance amplifiers, datasheet selection and trou…
