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Infineon Technologies CY8C6145AZI-S3F02
- Part No.:
- CY8C6145AZI-S3F02
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
CY8C6145AZI-S3F02.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,629
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Product details
Overview
CY8C6145AZI-S3F02 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 MCU optimized for secure, ultra-low-power IoT edge nodes. It integrates 512 KB flash, 256 KB SRAM, hardware cryptography (AES-256, ECC, TRNG), CAN FD, USB FS, and capacitive sensing (CSD) with SmartSense tuning. Operates from 1.7–3.6 V with Deep Sleep current as low as 7 µA (64 KB SRAM retained), targeting battery-powered sensor hubs and industrial gateways.
For engineers reviewing the CY8C6145AZI-S3F02 datasheet, CY8C6145AZI-S3F02 pinout, CY8C6145AZI-S3F02 application, or CY8C6145AZI-S3F02 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip DC-DC converter (<1 µA quiescent), QSPI XIP with 4 KB cache, and integrated CAN FD + USB Full-Speed in a single die.
Technical Context
This MCU implements a tightly coupled dual-CPU architecture where the Cortex-M4F handles application processing and real-time control, while the Cortex-M0+ is dedicated to system-level tasks including security boot, power management, and peripheral offload-precluding application use per design. The memory subsystem supports Read-While-Write (RWW) flash with two independent 8 KB CPU caches and programmable SRAM retention granularity down to 8 KB blocks.
Its clocking architecture combines an 8 MHz IMO (±2%), 32 kHz ILO, PLL/FLL frequency synthesis, and integer/fractional peripheral dividers-enabling precise timing for TCPWMs, ADC sampling, and USB frame synchronization. The SMIF interface delivers up to 320 Mbps quad-SPI throughput with on-the-fly AES-128 encryption for secure external code execution.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Cortex-M4F + 100-MHz Cortex-M0+, with MPU and separate flash/SRAM caches |
| Memory | 512 KB application flash (RWW), 32 KB AUXflash, 32 KB SFlash, 256 KB SRAM with programmable retention |
| Power Efficiency | Deep Sleep mode: 7 µA with 64 KB SRAM retention; active slope: 22 µA/MHz @ 0.9 V (M4) |
| Analog Peripherals | 12-bit 2-Msps SAR ADC (16-channel sequencer, averaging), 2 LP comparators (active in Deep Sleep), integrated temp sensor |
| Digital Interfaces | 7 SCBs (SPI/I²C/UART), 1 Deep Sleep SCB, USB Full-Speed device, CAN FD controller, SD/eMMC host, QSPI/SMIF with XIP & encryption |
| Security | Hardware crypto accelerator (AES-256, SHA-256, ECC), TRNG, boot authentication, 8 protection contexts, debug disable |
| Capacitive Sensing | CAPSENSE™ CSD subsystem with >100 dB SNR, liquid tolerance, self/mutual modes, and automatic SmartSense tuning |
Pinout & Package
Package: 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch), 64 GPIOs, including 2 Smart I/O ports (8 pins), 2 overvoltage-tolerant (OVT) pins, and dedicated SWD/JTAG debug pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]–P0[7] | GPIO Bank 0 | Programmable drive strength/slew rate; supports Smart I/O Boolean logic during Deep Sleep |
| P1[0]–P1[7] | GPIO Bank 1 | Includes two OVT-capable pins (P1[0], P1[1]) for direct connection to 5 V buses without level shifters |
| SWDIO / SWCLK | Debug Interface | 2-pin Serial Wire Debug (SWD) for programming and real-time trace; accessible in all non-Hibernate modes |
| VDDIO / VSSIO | I/O Power Domain | Configurable 1.7–3.6 V supply; independent of core voltage (VDDD) to support mixed-voltage interfacing |
| VDDD / VSSD | Core Power Domain | Supplies both CPUs and digital logic; supports dynamic voltage scaling between 0.9 V and 1.1 V for power optimization |
| USB_DP / USB_DM | USB Full-Speed PHY | Dedicated differential pair compliant with USB 2.0 FS signaling; internal termination and pull-up control |
| CAN_TX / CAN_RX | CAN FD Transceiver Interface | Direct connection to external CAN transceiver; supports ISO 11898-1:2015 FD frames up to 5 Mbps |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Voltage Core Operation | Runtime-selectable 0.9 V or 1.1 V CPU supply enables fine-grained trade-off between performance (150 MHz M4 @ 1.1 V) and ultra-low active current (22 µA/MHz @ 0.9 V) |
| Secure Boot & Runtime Protection | Hardware-enforced authentication using SHA-256 hashing of signed firmware images; debug/test paths permanently disableable via eFuse |
| Smart I/O in Deep Sleep | Two 8-pin Smart I/O ports execute Boolean logic (AND/OR/XOR) on GPIO states without waking CPUs-ideal for wake-on-event sensor fusion |
| Integrated CAN FD + USB FS | Single-die support for automotive-grade fieldbus (CAN FD up to 5 Mbps) and PC connectivity (USB FS) eliminates need for companion transceivers or bridges |
| Capacitive Sensing with SmartSense | Self-calibrating CSD engine achieves >100 dB SNR and robust operation under water or condensation-no manual tuning required in production |
Applications
| Industrial Sensor Node | Smart Home Hub |
|---|---|
|
Use Scenario: Battery-powered wireless node monitoring temperature, humidity, and vibration in factory environments with 10-year lifespan. IC Role / Device Role / Timing Role: Primary MCU executing sensor fusion, BLE advertising, and secure OTA updates; uses Deep Sleep + Smart I/O to wake only on threshold breach. Use Value: 7 µA Deep Sleep with 64 KB SRAM retention extends battery life; on-chip TRNG and AES-256 ensure firmware integrity against cloning. |
Use Scenario: Central gateway aggregating Zigbee, Matter-over-Thread, and Bluetooth LE devices while bridging to cloud via Wi-Fi/Ethernet. IC Role / Device Role / Timing Role: Dual-CPU orchestrator: M4 runs protocol stacks and local decision logic; M0+ manages USB HID emulation and secure boot verification. Use Value: Integrated USB FS + CAN FD enables simultaneous PC configuration and legacy appliance control; CAPSENSE™ supports touch-enabled UI without extra ICs. |
| Medical Wearable | Automotive Body Controller |
|
Use Scenario: ECG patch with dry electrodes, motion compensation, and encrypted data streaming to smartphone via BLE. IC Role / Device Role / Timing Role: Real-time signal acquisition via 2-Msps SAR ADC with 16-channel sequencer; M4 performs FIR filtering and HRV analysis. Use Value: On-chip temperature sensor calibrates ADC offset drift; hardware crypto accelerates BLE pairing and data signing without CPU overhead. |
Use Scenario: Door module controlling window lift, mirror fold, and interior lighting with LIN/CAN FD communication and anti-pinch safety logic. IC Role / Device Role / Timing Role: CAN FD endpoint with configurable bit timing; TCPWMs generate precise PWM for motor control with comparator-triggered kill signals. Use Value: Integrated CAN FD PHY interface reduces BOM count; 12 TCPWMs support center-aligned PWM for smooth motor ramping and fault-safe shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WB55RG | Single Cortex-M4 + Cortex-M0+ radio MCU; lacks CAN FD, integrated DC-DC, and CAPSENSE™; BLE 5.0 + IEEE 802.15.4 only | Better suited for pure wireless sensor nodes without wired fieldbus or analog-intensive front ends | Choose when RF integration outweighs need for CAN FD, high-resolution ADC, or capacitive touch |
| NXP KW45B41Z | ARM Cortex-M33 + M0+; includes BLE 5.2 and IEEE 802.15.4 but no USB, CAN FD, or hardware crypto acceleration beyond AES-128 | Targeted at cost-sensitive medical and asset tracking; limited analog capability (12-bit ADC, no CSD) | Prefer for BLE-centric designs requiring PSA Level 3 certification but not industrial I/O or secure boot enforcement |
Compared with STM32WB55RG and KW45B41Z, CY8C6145AZI-S3F02 uniquely combines CAN FD, USB FS, hardware-accelerated crypto, and CAPSENSE™ CSD in one ultra-low-power dual-core package-making it optimal for converged wired/wireless IoT edge controllers requiring analog sensing, fieldbus, and PC connectivity.
Availability
CY8C6145AZI-S3F02 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home gateways, medical wearables, and automotive body controllers requiring stable component supply across multi-year production cycles.
Supply support for CY8C6145AZI-S3F02 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, and security solutions, with global manufacturing and R&D infrastructure.
This device belongs to the PSOC™ 61 family-designed specifically for secure, battery-operated IoT endpoints requiring concurrent wireless connectivity, analog sensing, and real-time control without external co-processors.
FAQ
Does CY8C6145AZI-S3F02 support JTAG debugging?
No-this part uses Serial Wire Debug (SWD) exclusively. The SWDIO and SWCLK pins provide full debug access including breakpoints, memory inspection, and real-time trace. JTAG is not implemented; attempting JTAG protocols will fail. SWD is compatible with standard ARM debug probes (e.g., Segger J-Link, ST-Link v3).
What is the maximum operating frequency of the Cortex-M4F core?
The Cortex-M4F core operates at up to 150 MHz when powered at 1.1 V. At 0.9 V, maximum frequency is reduced to 100 MHz to maintain timing closure and power efficiency. Frequency scaling is controlled by the System Clock Configuration block and requires corresponding voltage domain adjustment via the PMU.
Can the on-chip DC-DC converter power external circuitry?
No-the integrated buck converter is strictly for internal core (VDDD) and analog (VCCD) supplies. Its output is not exposed to pins and cannot source current to external loads. External peripherals must be powered from dedicated regulators or LDOs connected to VDDIO or auxiliary rails.
Is CAPSENSE™ CSD supported in Deep Sleep mode?
Yes-CSD scanning can operate autonomously in Deep Sleep mode using the low-power comparator and dedicated CSD sequencer. No CPU wake-up is required; results are stored in dedicated SRAM regions and trigger interrupts upon completion or threshold violation.
CY8C6145AZI-S3F02 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-LQFP
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4F
- Core Size:
- 32-Bit
- Speed:
- 150MHz
- Connectivity:
- eMMC/SD/SDIO, FIFO, I2C, IrDA, LINbus, Microwire, QSPI, SmartCard, SPI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, DMA, LCD, LVD, POR, PWM, Temp Sensor, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x8b, 16x10/12b SAR, Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6145AZI-S3F02 FAQ
1.How can I place an order for CY8C6145AZI-S3F02 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6145AZI-S3F02 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6145AZI-S3F02 reliable?
The price and inventory of CY8C6145AZI-S3F02 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6145AZI-S3F02 is usually 5 days.
3.What payment methods are accepted for CY8C6145AZI-S3F02?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6145AZI-S3F02 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6145AZI-S3F02?
CY8C6145AZI-S3F02 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6145AZI-S3F02 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6145AZI-S3F02?
For technical support, including CY8C6145AZI-S3F02 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6145AZI-S3F02 requirements.
6.How does Aetrix verify that CY8C6145AZI-S3F02 is sourced from the original manufacturer or authorized distributors?
All CY8C6145AZI-S3F02 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6145AZI-S3F02 meets industry standards.
7.What is the process for return or replacement of CY8C6145AZI-S3F02?
All CY8C6145AZI-S3F02 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6145AZI-S3F02, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6145AZI-S3F02 part is unused and in its original packaging.
Return procedure for CY8C6145AZI-S3F02:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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