Infineon Technologies CY8C6145AZI-S3F42

Overview

CY8C6145AZI-S3F42 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller designed for secure, ultra-low-power IoT edge nodes. It integrates 512 KB flash, 256 KB SRAM, hardware cryptography accelerator, CAN FD interface, and capacitive sensing (CapSense™), operating from 1.7–3.6 V with Deep Sleep current as low as 7 µA (64 KB SRAM retained).

For engineers reviewing the CY8C6145AZI-S3F42 datasheet, CY8C6145AZI-S3F42 pinout, CY8C6145AZI-S3F42 application, or CY8C6145AZI-S3F42 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip DC-DC converter (<1 µA quiescent), QSPI XIP with encryption, and integrated CapSense™ with SmartSense™ auto-tuning.

Technical Context

The device implements a tightly coupled dual-CPU architecture where the Cortex-M4F handles application processing at up to 150 MHz with FPU and MPU, while the Cortex-M0+ (100 MHz) is reserved exclusively for system-level functions including security boot, power management, and peripheral offload - not user application code. Both cores operate at selectable 1.1 V or 0.9 V supply voltages to optimize active current.

Its programmable analog-digital subsystem includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and averaging, two Deep Sleep-capable comparators, and a dedicated CapSense™ sigma-delta engine supporting self/mutual sensing with liquid tolerance. Clocking combines IMO (8 MHz ±2%), ILO (32 kHz), PLL/FLL, and fractional dividers for precise peripheral timing.

Key Specifications

Pinout & Package

This device is packaged in a 100-pin TQFP (14 × 14 mm, 0.5 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 pins total) enabling Boolean logic during Deep Sleep.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6145AZI-S3F42, CY8C6247FDI-D52 trades CAN FD for integrated BLE and higher flash density, while STM32WB55RGV offers lower BOM cost but demands external circuitry for touch and encrypted XIP - making CY8C6145AZI-S3F42 optimal for secure, sensor-rich, wired-edge applications.

Availability

CY8C6145AZI-S3F42 is available at Aetrix Electronics and suitable for industrial predictive maintenance nodes, medical wearable patches, smart home sensor hubs, and automotive cabin controllers requiring stable component supply across extended product lifecycles.

Supply support for CY8C6145AZI-S3F42 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive ICs, and secure microcontrollers, with global manufacturing and quality certifications including IATF 16949 and ISO 9001.

This device belongs to the PSOC™ 61 MCU product line - engineered specifically for ultra-low-power, security-critical IoT edge devices requiring integrated analog programmability, hardware crypto, and deterministic real-time response.

FAQ

Is the Cortex-M0+ core available for user application code?

No. The Cortex-M0+ in CY8C6145AZI-S3F42 is reserved exclusively for system-level functions including secure boot, power management, interrupt dispatching, and peripheral offload. Application firmware must run solely on the Cortex-M4F core, which operates at up to 150 MHz with FPU and MPU support.

Does this device support execute-in-place (XIP) from external flash?

Yes. The integrated Quad-SPI/SMIF interface supports XIP from external quad-SPI flash with on-the-fly AES-128 decryption and a dedicated 4 KB cache. This enables low-power, high-speed firmware execution without loading code into internal RAM, reducing active current and memory footprint.

What is the maximum clock frequency of the CAN FD peripheral?

The CAN FD block supports data bit rates up to 5 Mbps in fast-phase mode, compliant with ISO 11898-1:2015. It uses dedicated CAN_FD_H/CAN_FD_L pins and operates independently of CPU load, with hardware message filtering and TX/RX FIFOs managed by the M0+ subsystem.

How does CapSense™ achieve liquid tolerance on this MCU?

Liquid tolerance is achieved through the dedicated CapSense™ CSD (capacitive sigma-delta) hardware engine, which uses spread-spectrum modulation, shield-driven sensing, and automatic baseline compensation. SmartSense™ firmware performs real-time tuning to reject water-induced capacitance shifts while maintaining >100:1 signal-to-noise ratio for true touch detection.