Infineon Technologies CY8C6145AZI-S3F72

Overview

CY8C6145AZI-S3F72 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 MCU optimized for secure, ultra-low-power IoT edge nodes. It integrates 512 KB flash, 256 KB SRAM, hardware cryptography accelerator, CAN FD, USB Full-Speed, and CAPSENSE™ capacitive sensing-enabling battery-powered smart sensors and industrial controllers with <7 µA Deep Sleep current and 150 MHz M4F performance.

For engineers reviewing the CY8C6145AZI-S3F72 datasheet, CY8C6145AZI-S3F72 pinout, CY8C6145AZI-S3F72 application, or CY8C6145AZI-S3F72 equivalent, key selection criteria include dual-CPU power management (22 µA/MHz @ 0.9 V), on-chip DC-DC buck (<1 µA quiescent), QSPI XIP with hardware encryption, and 64 GPIOs with Smart I/O Boolean logic in Deep Sleep.

Technical Context

The device implements a tightly coupled dual-CPU architecture where the Cortex-M4F handles application processing and real-time control while the Cortex-M0+ manages system-level functions including security boot, power mode transitions, and peripheral arbitration-without user application access. Memory subsystem includes RWW flash with two 8-KB CPU-specific caches and programmable SRAM retention granularity down to 64 KB.

Clocking combines an 8-MHz IMO (±2%), 32-kHz ILO, PLL/FLL frequency synthesis, and integer/fractional dividers to feed independent clock domains for CPU, analog, and digital peripherals. The SMIF supports quad-SPI XIP with 4-KB cache and on-the-fly AES-128 decryption, enabling secure external code execution at up to 320 Mbps.

Key Specifications

Pinout & Package

This device is packaged in a 72-pin TQFP (10 × 10 mm, 0.5 mm pitch) with 64 general-purpose I/Os, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 pins total) supporting Boolean logic in Deep Sleep.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with STM32WB55RGV and RA6M5GFP, CY8C6145AZI-S3F72 uniquely delivers CAN FD + QSPI XIP + CAPSENSE™ + sub-7-µA Deep Sleep in one die-making it optimal for secure, sensor-rich, battery-operated edge controllers where mixed-signal integration and autonomous low-power logic reduce system-level component count.

Availability

CY8C6145AZI-S3F72 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home hubs, medical wearables, and automotive body control modules requiring stable component supply across multi-year production cycles.

Supply support for CY8C6145AZI-S3F72 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive ICs, and secure microcontrollers-with annual revenue exceeding €14 billion and global manufacturing in Dresden, Villach, and Kulim.

This part belongs to the PSOC™ 61 MCU product line, engineered specifically for secure, ultra-low-power IoT endpoints that demand integrated analog, programmable logic, and hardware-enforced trust-targeting battery-operated edge intelligence in industrial, medical, and consumer domains.

FAQ

Does CY8C6145AZI-S3F72 support JTAG debugging?

Yes-it features a SWJ-DP (Serial Wire JTAG Debug Port) with full ARM CoreSight support, enabling real-time trace, breakpoint debugging, and memory inspection for both Cortex-M4F and Cortex-M0+ cores. The 32-bit Silicon ID is accessible via SWJ, with die revision encoded in the MSB and manufacturer ID "069" in the LSBs.

What is the maximum operating frequency of the QSPI interface?

The QSPI interface supports up to 320 Mbps throughput in quad mode, achieved using a 80-MHz SMIF clock derived from the PLL. This enables zero-wait-state XIP from external flash and meets timing requirements for real-time firmware execution in resource-constrained edge devices.

Can the CAPSENSE™ subsystem operate during Deep Sleep mode?

Yes-CAPSENSE™ CSD hardware runs autonomously in Deep Sleep mode using the 32-kHz ILO clock, detecting touch or proximity events and generating interrupts without waking the CPU. SmartSense auto-tuning remains active, maintaining accuracy across temperature and humidity variations.

Is the on-chip DC-DC converter mandatory for operation?

No-the device supports direct LDO operation from 1.7–3.6 V, but the integrated DC-DC buck is recommended for battery-powered designs: it delivers >85% efficiency at 10–100 mA loads and reduces quiescent current to <1 µA, extending runtime significantly versus external regulators.