Infineon Technologies CY8C6145FNI-S3F11T

Overview

CY8C6145FNI-S3F11T from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller designed for secure, ultra-low-power IoT edge nodes. It integrates 512 KB flash, 256 KB SRAM, hardware cryptography acceleration, CAN FD, USB Full-Speed, and CAPSENSE™ capacitive sensing-enabling battery-operated smart sensors and connected industrial controllers.

For engineers reviewing the CY8C6145FNI-S3F11T datasheet, CY8C6145FNI-S3F11T pinout, CY8C6145FNI-S3F11T application, or CY8C6145FNI-S3F11T equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), Deep Sleep current (7 µA with 64 KB SRAM retention), integrated CAN FD + USB, and hardware TRNG/secure boot architecture.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles application processing at up to 150 MHz while the Cortex-M0+ (100 MHz) manages system-level tasks including security services and peripheral offload-its firmware access restricted per platform policy. Memory coherency is maintained via shared bus matrix and three DMA controllers.

Its programmable analog-digital fabric includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and averaging, two Deep Sleep-capable comparators, and CAPSENSE™ CSD with SmartSense auto-tuning. Clocking combines IMO (8 MHz ±2%), ILO (32 kHz), PLL/FLL, and fractional dividers for precise peripheral timing.

Key Specifications

Pinout & Package

This device is housed in a 100-pin TQFP package (14 × 14 mm, 0.5 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 total I/Os) supporting Boolean logic during Deep Sleep.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6145FNI-S3F11T, CY8C6247FMI-D52 trades ultra-low Deep Sleep for memory headroom and package compactness, while STM32H743VI delivers higher clock speed at the cost of integrated sensing, dual-core isolation, and hardware CAN FD-making the CY8C6145FNI-S3F11T optimal for battery-constrained, sensor-rich, and security-sensitive IoT endpoints.

Availability

CY8C6145FNI-S3F11T is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home hubs, medical wearables, and automotive body controllers requiring stable component supply across multi-year production cycles.

Supply support for CY8C6145FNI-S3F11T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, and secure embedded solutions, with global manufacturing and R&D infrastructure.

This part belongs to the PSOC™ 61 MCU product line-designed specifically for secure, energy-efficient IoT edge devices combining programmable analog/digital fabric with Arm dual-core processing and hardware-rooted trust.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6145FNI-S3F11T?

The Cortex-M4F core operates at up to 150 MHz under 1.1 V core voltage and 100 MHz under 0.9 V core voltage. Frequency scaling is user-configurable via the clock tree and voltage regulator settings, with performance validated across industrial temperature range (–40°C to +85°C) per datasheet Rev. *G.

Does CY8C6145FNI-S3F11T support CAN FD without an external transceiver?

No. The device integrates a CAN FD controller compliant with ISO 11898-1:2015, but requires an external CAN FD physical-layer transceiver (e.g., Infineon TLE9471-2ES) for bus interfacing. The CAN_TX and CAN_RX pins provide differential logic-level signals only.

How many GPIOs support overvoltage tolerance, and what is their rating?

Two GPIOs-P1[0] and P1[1]-are overvoltage-tolerant (OVT) and rated to 5.5 V regardless of VDD (1.7–3.6 V). They support direct interface with 5 V logic or automotive 12 V signals through appropriate resistive dividers, as confirmed in the "GPIO Electrical Specifications" section of datasheet 002-30703 Rev. *G.

Is the CAPSENSE™ subsystem capable of operating during Deep Sleep mode?

Yes. The CAPSENSE™ CSD hardware subsystem-including sigma-delta modulator, IDACs, and scanning logic-operates fully in Deep Sleep mode. It can autonomously scan up to 63 segments, trigger wake-on-touch, and maintain liquid tolerance without CPU involvement, as documented in the "CAPSENSE™ Subsystem" functional description.