Infineon Technologies CY8C6145LQI-S3F02

Overview

CY8C6145LQI-S3F02 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 MCU optimized for secure, ultra-low-power IoT edge nodes. It integrates 512-KB flash, 256-KB SRAM, hardware cryptography accelerator, CAN FD interface, and capacitive sensing (CAPSENSE™), operating from 1.7–3.6 V with Deep Sleep current as low as 7 µA (64-KB SRAM retained). Used in battery-powered smart sensors and industrial gateways requiring secure firmware updates and real-time sensor fusion.

For engineers reviewing the CY8C6145LQI-S3F02 datasheet, CY8C6145LQI-S3F02 pinout, CY8C6145LQI-S3F02 application, or CY8C6145LQI-S3F02 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4 core), on-chip DC-DC converter (<1 µA quiescent), CAN FD compliance, XIP-capable Quad-SPI interface, and hardware TRNG + eFuse-based secure boot.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles application processing and real-time control, while the Cortex-M0+ is reserved exclusively for system-level functions including security services, power management, and peripheral offload - not user-accessible. Both cores operate at independent voltages (0.9 V or 1.1 V) with dedicated flash caches and DMA controllers.

Its programmable analog-digital architecture includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and averaging, two Deep Sleep-capable comparators, CAPSENSE™ sigma-delta CSD engine with SmartSense auto-tuning, and a dedicated CAN FD block supporting ISO 11898-1:2015 with bit rates up to 5 Mbps and flexible data field lengths.

Key Specifications

Pinout & Package

Package: 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch), 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 total I/Os with Boolean logic in Deep Sleep).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6145LQI-S3F02, CY8C6247FDI-D52 trades CAN FD for AI acceleration and larger memory, while STM32U585QII6 offers stronger formal security certification at the cost of programmable analog flexibility and ultra-low-power Deep Sleep features.

Availability

CY8C6145LQI-S3F02 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home hubs, automotive body controllers, and medical wearables requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for CY8C6145LQI-S3F02 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global manufacturing and quality certifications including IATF 16949 and ISO 9001.

This part belongs to the PSOC™ 61 MCU product line, designed specifically for secure, ultra-low-power IoT endpoints that require integrated analog sensing, hardware-enforced security, and heterogeneous compute for edge intelligence.

FAQ

Is the Cortex-M0+ core accessible to user firmware?

No. The Cortex-M0+ core in CY8C6145LQI-S3F02 is reserved exclusively for system-level functions including secure boot, power management, and peripheral offload. It cannot be programmed directly by application firmware - only the Cortex-M4F core is user-accessible for application code execution.

Does this MCU support CAN FD without an external transceiver?

No. The CY8C6145LQI-S3F02 includes a CAN FD protocol controller and physical layer (PHY) driver, but requires an external CAN FD transceiver (e.g., TJA1044T) for bus connection. The internal circuitry provides differential signaling and bit timing compliance per ISO 11898-1:2015.

What is the maximum supported Quad-SPI flash density for XIP operation?

The SMIF interface supports external Quad-SPI flash up to 256 MB (2 Gb) in XIP mode. Address space is mapped into the M4 core's instruction bus with hardware AES decryption enabled, and the 4-KB cache buffers instruction fetches to minimize latency and reduce active power during code execution.

How is CAPSENSE™ performance validated in presence of water or sweat?

CAPSENSE™ CSD implementation achieves >100 dB signal-to-noise ratio and is validated per IEC 60529 IPX7 for liquid tolerance. Hardware SmartSense auto-tuning dynamically adjusts scan parameters (frequency, IDAC, averaging) to maintain baseline stability and reject moisture-induced capacitance drift without firmware intervention.