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Infineon Technologies CY8C6145LQI-S3F42

Part No.:
CY8C6145LQI-S3F42
Manufacturer:
Infineon Technologies
Category:
Microcontrollers
Package:
68-VFQFN Exposed Pad
Datasheet:
AetrixCY8C6145LQI-S3F42.pdf
Description:
IC MCU 32BIT 512KB FLASH 68QFN
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,354

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Product details

Overview

CY8C6145LQI-S3F42 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 MCU with 512 KB flash, 256 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography accelerator - designed for secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion, wireless coexistence, and firmware-over-the-air (FOTA) updates.

For engineers reviewing the CY8C6145LQI-S3F42 datasheet, CY8C6145LQI-S3F42 pinout, CY8C6145LQI-S3F42 application, or CY8C6145LQI-S3F42 equivalent, this device supports concurrent BLE/Wi-Fi coexistence via programmable digital logic, delivers 7 µA Deep Sleep current with 64 KB SRAM retention, and integrates CAPSENSE™ for touch/HMI in battery-powered industrial gateways and smart sensors.

Technical Context

The device implements a tightly coupled dual-CPU subsystem: the 150-MHz Cortex-M4F handles application processing and cryptographic operations, while the dedicated 100-MHz Cortex-M0+ manages system-level tasks including power mode transitions, interrupt routing, and secure boot - with no application access to the M0+ core. Both CPUs operate at either 1.1 V (40/20 µA/MHz) or 0.9 V (22/15 µA/MHz) for dynamic power scaling.

Its programmable analog-digital fabric includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and result averaging, two deep-sleep-capable comparators, and a capacitive sigma-delta (CSD) sensing engine with SmartSense auto-tuning - enabling simultaneous environmental sensing and low-power HMI in a single chip without external signal conditioning.

Key Specifications

Parameter Value and Actual Design Meaning
CPU Cores Dual-core: 150-MHz Arm Cortex-M4F + 100-MHz Cortex-M0+, with independent MPUs and voltage scaling (0.9 V / 1.1 V)
Memory 512 KB flash (RWW), 256 KB SRAM (programmable retention), 32 KB AUXflash, 32 KB SFlash, 2×8 KB CPU caches
Low-Power Performance 7 µA Deep Sleep current with 64 KB SRAM retention; on-chip DC-DC buck converter with <1 µA quiescent current
Analog Peripherals 12-bit 2-Msps SAR ADC (16-channel sequencer, differential/single-ended, result averaging); 2 LP comparators active in Deep Sleep
Digital Interfaces 1× CAN FD, 1× USB Full-Speed device, 7× SCBs (6 configurable as SPI/I²C/UART, 1 Deep Sleep SCB), QSPI/SMIF with XIP & AES encryption
Sensing & HMI CAPSENSE™ CSD engine with liquid tolerance, proximity support, and hardware SmartSense tuning; segment LCD driver (63 seg × 8 com)
Security Hardware crypto accelerator (AES-128/256, SHA-256, ECC, TRNG); boot authentication via hardware hashing; 8 protection contexts

Pinout & Package

This device is packaged in a 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 total I/Os) supporting Boolean logic during Deep Sleep.

Pin/Terminal Circuit Role Design Meaning
P0[0]–P0[7] GPIO Bank 0 Programmable drive modes, slew rates; supports Smart I/O Boolean logic in Deep Sleep
P1[0]–P1[7] GPIO Bank 1 Includes two OVT pins (P1[0], P1[1]) tolerant to 5.5 V in 1.7–3.6 V operation
USB_DP / USB_DM USB Full-Speed Interface Dedicated differential pair compliant with USB 2.0 FS; internal PHY, no external termination required
CAN_TX / CAN_RX CAN FD Physical Layer Direct connection to external CAN transceiver; supports bit rates up to 5 Mbps with flexible data phase
VDDIO0 / VDDIO1 I/O Power Supplies Independent 1.7–3.6 V domains per bank; enables mixed-voltage interfacing (e.g., 1.8 V logic + 3.3 V sensors)
XRES External Reset Input Active-low asynchronous reset with internal pull-up; debounced internally for robust system initialization

Key Features

Feature Design Value
Dual-Voltage Core Operation Runtime-selectable 0.9 V / 1.1 V core supply enables 22 µA/MHz (M4) or 40 µA/MHz (M4) active power trade-off
Secure Boot & Runtime Protection Hardware-based SHA-256 hashing of firmware images; debug/test paths disableable; 8 configurable memory protection contexts
Deep Sleep Programmability Smart I/O ports retain Boolean logic execution and GPIO state during Deep Sleep; LP comparators wake CPU on threshold crossing
Integrated SMIF with XIP Execute-in-place from external quad-SPI flash with 4 KB cache and on-the-fly AES-128 decryption - eliminates boot latency and external RAM
CAPSENSE™ Hardware Subsystem Dedicated CSD block with automatic calibration, noise immunity up to 20 Vpp, and mutual/self-capacitance support - no host CPU overhead

Applications

Industrial Sensor Node Smart Home Gateway

Use Scenario: Battery-powered vibration/temperature node in predictive maintenance systems with BLE telemetry and local FFT preprocessing.

IC Role / Device Role / Timing Role: Dual-core real-time sensor acquisition (M4) + low-power BLE stack management (M0+); precise timestamping via MCWDT and FLL-stabilized clocks.

Use Value: 7 µA Deep Sleep extends 2-AA battery life beyond 5 years; integrated crypto enables signed OTA firmware updates without external secure element.

Use Scenario: Multi-protocol hub aggregating Zigbee, Matter-over-Thread, and BLE devices with local voice assistant trigger detection.

IC Role / Device Role / Timing Role: Central protocol translator and CAPSENSE™-enabled physical button interface; USB FS used for diagnostics and firmware recovery.

Use Value: Smart I/O offloads button debounce and LED sequencing in Deep Sleep; CAN FD connects to legacy building automation controllers.

Medical Wearable Automotive Cabin Controller

Use Scenario: ECG patch with dry-electrode sensing, motion artifact compensation, and encrypted Bluetooth LE transmission to smartphone.

IC Role / Device Role / Timing Role: SAR ADC oversampling + digital filtering on M4; CAPSENSE™ detects electrode contact quality; TRNG seeds session keys.

Use Value: On-chip temperature sensor calibrates ADC offset drift; 64-byte backup domain retains RTC across power cycles for compliance logging.

Use Scenario: Seat occupancy and climate control panel with touch sliders, ambient light sensing, and LIN/CAN gateway functions.

IC Role / Device Role / Timing Role: CAPSENSE™ slider + ambient light ADC on shared channels; CAN FD communicates with body control module; segment LCD displays HVAC status.

Use Value: Segment LCD driver operates in Deep Sleep (32 kHz ILO clock), reducing display power by >90% vs. external controller.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Alternative Part Technical Difference Application Difference Selection Advice
RP2040 No hardware crypto accelerator, no CAN FD, no Deep Sleep SCB or LP comparators; relies on software AES and external transceivers Lacks integrated security and automotive-grade peripherals; suitable only for cost-sensitive consumer prototypes without certification requirements Choose RP2040 only when BOM cost is primary constraint and FIPS/UL 2900-1 compliance is not required
STM32U585 Single-core Cortex-M33 with TrustZone; lower SRAM (3 MB vs. 256 KB), no CAPSENSE™, no Smart I/O; higher Deep Sleep current (1.4 µA vs. 7 µA) Stronger isolation for certified secure boot but lacks programmable analog/digital fabric for sensor fusion acceleration Prefer STM32U585 when PSA Certified Level 3 is mandatory and application requires large external memory via Octo-SPI

Compared with RP2040 and STM32U585, CY8C6145LQI-S3F42 uniquely combines dual-core deterministic real-time response, hardware-accelerated crypto, and programmable analog-digital resources - enabling single-chip sensor fusion, secure connectivity, and ultra-low-power HMI without external ICs.

Availability

CY8C6145LQI-S3F42 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home gateways, medical wearables, and automotive cabin controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for CY8C6145LQI-S3F42 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global R&D centers and ISO/TS 16949-certified manufacturing.

This device belongs to the PSOC™ 61 MCU product line - engineered specifically for secure, ultra-low-power IoT endpoints that demand concurrent wireless protocols, hardware-enforced trust, and integrated analog-sensing capability without compromising real-time determinism.

FAQ

Does CY8C6145LQI-S3F42 support JTAG debugging?

Yes - it features a SWJ-DP (Serial Wire JTAG Debug Port) with full ARM CoreSight support, enabling real-time trace, breakpoint debugging, and memory inspection for both Cortex-M4F and Cortex-M0+ cores. The JTAG ID is a fixed 32-bit value derived from die revision, part number, and manufacturer code (0x069), accessible via SWD interface without requiring external debug probe configuration.

What is the maximum operating frequency of the CAN FD peripheral?

The integrated CAN FD block supports data bit rates up to 5 Mbps in the data phase and nominal bit rates up to 1 Mbps, compliant with ISO 11898-1:2015. It uses dedicated clock dividers tied to the FLL or PLL output, and requires an external CAN transceiver; no internal termination or bus arbitration logic is included.

Can the SAR ADC perform continuous conversions during Deep Sleep mode?

No - the 12-bit SAR ADC requires active CPU clocking and cannot operate autonomously in Deep Sleep. However, the two low-power comparators remain fully functional in Deep Sleep and can trigger wake events or generate interrupts upon threshold crossing, enabling ultra-low-power conditional sensing.

Is the USB Full-Speed interface self-powered or bus-powered?

The USB Full-Speed interface is strictly device-side and bus-powered - it draws VBUS (5 V) from the host and regulates internally to 3.3 V for USB PHY operation. No external VBUS detection circuitry is needed; the device supports suspend/resume signaling and remote wakeup via dedicated USB registers mapped in the system control block.

CY8C6145LQI-S3F42 Specifications

Product attributes
Attribute value
Manufacturer:
Infineon Technologies
Package/Case:
68-VFQFN Exposed Pad
Series:
PSOC™ 6
Packaging:
Tray
Product Status:
Active
Programmable:
Not Verified
Core Processor:
ARM® Cortex®-M4F
Core Size:
32-Bit
Speed:
150MHz
Connectivity:
eMMC/SD/SDIO, FIFO, I2C, IrDA, LINbus, Microwire, QSPI, SmartCard, SPI, SSP, UART/USART, USB
Peripherals:
Brown-out Detect/Reset, CapSense, Crypto - AES, DMA, LCD, LVD, PMC, POR, PWM, RSA, SHA, Temp Sensor, TRNG, WDT
Number of I/O:
53
Program Memory Size:
512KB (512K x 8)
Program Memory Type:
FLASH
EEPROM Size:
-
RAM Size:
256K x 8
Voltage - Supply (Vcc/Vdd):
1.7V ~ 3.6V
Data Converters:
A/D 16x8b, 16x10/12b SAR, Sigma-Delta; D/A 2x7/8b
Oscillator Type:
External, Internal
Operating Temperature:
-40°C ~ 85°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:

CY8C6145LQI-S3F42 FAQ

1.How can I place an order for CY8C6145LQI-S3F42 through Aetrix?

Please submit a Request for Quotation (RFQ) for CY8C6145LQI-S3F42 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for CY8C6145LQI-S3F42 reliable?

The price and inventory of CY8C6145LQI-S3F42 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6145LQI-S3F42 is usually 5 days.

3.What payment methods are accepted for CY8C6145LQI-S3F42?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6145LQI-S3F42 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for CY8C6145LQI-S3F42?

CY8C6145LQI-S3F42 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your CY8C6145LQI-S3F42 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for CY8C6145LQI-S3F42?

For technical support, including CY8C6145LQI-S3F42 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6145LQI-S3F42 requirements.

6.How does Aetrix verify that CY8C6145LQI-S3F42 is sourced from the original manufacturer or authorized distributors?

All CY8C6145LQI-S3F42 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6145LQI-S3F42 meets industry standards.

7.What is the process for return or replacement of CY8C6145LQI-S3F42?

All CY8C6145LQI-S3F42 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6145LQI-S3F42, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The CY8C6145LQI-S3F42 part is unused and in its original packaging.

Return procedure for CY8C6145LQI-S3F42:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

CY8C6145LQI-S3F42 Tags

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