Infineon Technologies CY8C6145LQI-S3F62

Overview

CY8C6145LQI-S3F62 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 MCU optimized for secure, ultra-low-power IoT edge nodes, featuring 512 KB flash, 256 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography acceleration. It operates from 1.7–3.6 V, achieves 7 µA Deep Sleep current with 64 KB SRAM retention, and supports XIP from external QSPI flash at up to 320 Mbps.

For engineers reviewing the CY8C6145LQI-S3F62 datasheet, CY8C6145LQI-S3F62 pinout, CY8C6145LQI-S3F62 application, or CY8C6145LQI-S3F62 equivalent, key selection considerations include dual-CPU power efficiency trade-offs (22 µA/MHz @ 0.9 V M4), on-chip DC-DC quiescent current (<1 µA), CAN FD timing compliance, and Smart I/O Boolean logic availability in Deep Sleep mode.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles application processing and real-time control while the Cortex-M0+ is reserved exclusively for system-level functions including security boot, interrupt management, and peripheral arbitration - not user application code. Memory protection units (MPUs) are present on both cores, and inter-processor communication (IPC) uses dedicated hardware channels with mailbox semantics.

Clocking combines multiple independent sources: an 8-MHz IMO (±2%), 32-kHz ILO, crystal oscillators (16–35 MHz + 32 kHz), FLL for IMO multiplication, and PLL for high-frequency synthesis. All peripherals-including TCPWMs, SCBs, and SMIF-derive clocks via integer/fractional dividers with dynamic reconfiguration support during runtime.

Key Specifications

Pinout & Package

This device is packaged in a 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 total I/Os). Power domains include VDDIO (1.7–3.6 V), VDDD (core, 0.9/1.1 V selectable), and VBACKUP (for RTC and 64-byte backup memory).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6145LQI-S3F62, CY8C6247FDI-D52 trades CAN FD for expanded memory and USB flexibility, while STM32H743VI sacrifices ultra-low-power architecture and integrated analog front-end for higher clock speed and external memory bandwidth - making CY8C6145LQI-S3F62 uniquely balanced for battery-operated, sensor-rich, and security-critical edge nodes.

Availability

CY8C6145LQI-S3F62 is available at Aetrix Electronics and suitable for smart home sensor hubs, industrial predictive maintenance nodes, medical wearable patches, and automotive body control subsystems requiring stable component supply across long-lifecycle deployments.

Supply support for CY8C6145LQI-S3F62 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, security solutions, and embedded controllers, with global R&D centers and ISO/TS 16949-certified manufacturing.

This part belongs to the PSoC™ 61 MCU product line, designed specifically for secure, ultra-low-power IoT endpoints requiring integrated analog, programmable logic, and hardware-accelerated cryptography - not general-purpose computing or high-performance DSP.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6145LQI-S3F62?

The Cortex-M4F core operates at up to 150 MHz, with single-cycle multiply, floating-point unit (FPU), and memory protection unit (MPU) enabled. This frequency is achievable under 1.1-V core voltage and ambient temperatures up to 85°C, as validated in the device's electrical specifications table (Rev. *G, Section 6.2.2).

Does CY8C6145LQI-S3F62 support hardware-based secure boot?

Yes - it implements hardware-rooted secure boot using SHA-256 hashing of the boot image stored in protected flash. The ROM bootloader validates signature integrity before executing flash-resident firmware, and all debug/test interfaces (JTAG/SWD) can be permanently disabled via eFuse programming.

Can the Smart I/O blocks operate independently during Deep Sleep mode?

Yes - both Smart I/O ports (8 pins total) remain fully functional in Deep Sleep mode, performing Boolean logic (AND/OR/XOR) on input states and generating wake events without waking the CPU. This capability is confirmed in the "Smart I/O" section of the PSoC™ 61 Technical Reference Manual (TRM), Section 3.4.1.

Is CAN FD timing compliant with ISO 11898-1:2015 at 5 Mbps?

Yes - the integrated CAN FD block meets ISO 11898-1:2015 requirements for bit timing accuracy and synchronization at data rates up to 5 Mbps, with programmable sample point, propagation delay compensation, and loopback self-test mode verified in characterization testing per Infineon's CY8C61x5 Datasheet Rev. *G, Section 3.5.7.