Infineon Technologies CY8C6145LQI-S3F72

Overview

CY8C6145LQI-S3F72 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 61 microcontroller designed for secure, ultra-low-power IoT edge nodes. It integrates 512 KB flash, 256 KB SRAM, hardware cryptography acceleration, CAN FD, USB Full-Speed, and capacitive sensing (CAPSENSE™), operating from 1.7–3.6 V with Deep Sleep current as low as 7 µA (64 KB SRAM retained).

For engineers reviewing the CY8C6145LQI-S3F72 datasheet, CY8C6145LQI-S3F72 pinout, CY8C6145LQI-S3F72 application, or CY8C6145LQI-S3F72 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip DC-DC converter (<1 µA quiescent), QSPI XIP with 4 KB cache, and integrated CAPSENSE™ with SmartSense auto-tuning.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles application processing at up to 150 MHz with FPU and MPU, while the Cortex-M0+ (100 MHz) is reserved exclusively for system-level functions including security boot, power management, and peripheral arbitration - not user application code. Both cores support dynamic voltage scaling between 0.9 V and 1.1 V.

Its programmable analog-digital architecture includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and averaging, two Deep Sleep-capable comparators, and a dedicated CAPSENSE™ sigma-delta subsystem supporting self/mutual sensing with hardware-accelerated SmartSense tuning - all independently operable during system Deep Sleep mode.

Key Specifications

Pinout & Package

This device is packaged in a 72-pin QFN (7 mm × 7 mm, 0.4 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 total I/Os) enabling Boolean logic during Deep Sleep.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6145LQI-S3F72, CY8C6247FDI-D52 trades off power efficiency and analog integration for wireless capability, while STM32WBA52CGU6 sacrifices dual-core security features and CAPSENSE™ for BLE integration and lower entry cost - neither matches its combination of ultra-low-power Deep Sleep, hardware-accelerated touch, and CAN FD in a compact QFN.

Availability

CY8C6145LQI-S3F72 is available at Aetrix Electronics and suitable for smart home sensor hubs, industrial predictive maintenance nodes, medical wearables, and automotive cabin controllers requiring stable component supply, long-term lifecycle assurance, and qualified production traceability.

Supply support for CY8C6145LQI-S3F72 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power systems, automotive ICs, and secure microcontrollers, with global manufacturing and quality certifications including ISO/TS 16949 and ISO 9001.

This part belongs to the PSOC™ 61 MCU product line - engineered specifically for secure, battery-operated IoT endpoints demanding simultaneous low-power operation, rich analog sensing, and robust communication (CAN FD, USB, QSPI) without external components.

FAQ

Is the Cortex-M0+ core available for user application code?

No. The Cortex-M0+ in CY8C6145LQI-S3F72 is reserved exclusively for system-level functions including secure boot, power management, interrupt arbitration, and peripheral control. Application firmware must run solely on the Cortex-M4F core, which operates at up to 150 MHz with FPU and MPU support.

Does this device support execute-in-place (XIP) from external flash?

Yes. The integrated Quad-SPI/SMIF interface supports XIP from external quad-SPI flash with on-the-fly AES-128 decryption and a dedicated 4 KB instruction cache, enabling low-latency code execution while minimizing active power consumption during firmware fetch.

What is the minimum supply voltage for Deep Sleep mode with full SRAM retention?

The device maintains full 64 KB SRAM retention in Deep Sleep mode down to 1.7 V VDDD supply. At 1.7 V, Deep Sleep current remains ≤7 µA, verified per Infineon's 002-30703 Rev. *G datasheet Section 6.2.2 under "Device-level specifications".

Can CAPSENSE™ operate while the CPU is in Deep Sleep?

Yes. The CAPSENSE™ sigma-delta (CSD) subsystem operates autonomously during Deep Sleep mode using the internal low-speed oscillator (ILO). It supports self- and mutual-capacitance sensing, automatic SmartSense tuning, and wake-on-touch events without waking the CPU or consuming active-core current.