Infineon Technologies CY8C6244AZI-S4D93

Overview

CY8C6244AZI-S4D93 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 256 KB flash, 128 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography accelerators. It operates from 1.7 V to 3.6 V, achieves 7 µA Deep Sleep current with 64 KB SRAM retention, and supports XIP from external QSPI Flash at up to 320 Mbps-targeted for secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion and wireless coexistence.

For engineers reviewing the CY8C6244AZI-S4D93 datasheet, CY8C6244AZI-S4D93 pinout, CY8C6244AZI-S4D93 application, or CY8C6244AZI-S4D93 equivalent, key selection criteria include dual-CPU power-performance tradeoff, on-chip DC-DC buck efficiency (<1 µA quiescent), CAN FD timing compliance, and Secure Boot root-of-trust implementation in ROM.

Technical Context

The device integrates two tightly coupled CPUs: a 150-MHz Cortex-M4F with FPU and MPU, and a 100-MHz Cortex-M0+ with single-cycle multiply and MPU-both configurable for 1.1 V or 0.9 V core logic operation. Inter-processor communication uses hardware IPC channels with doorbell interrupts and shared memory.

Its clock system combines an 8-MHz IMO (±2%), 32-kHz ILO, programmable PLL/FLL, and on-chip crystal oscillators (16–35 MHz + 32 kHz), enabling dynamic frequency scaling across six power modes. The SMIF subsystem delivers 320 Mbps Quad-SPI throughput with on-the-fly AES encryption and 4-KB cache for XIP execution.

Key Specifications

Pinout & Package

Package: 80-pin Thin Quad Flat Package (TQFP), 12 mm × 12 mm body, 0.5 mm pitch, exposed thermal pad (EP), RoHS-compliant, rated for –40°C to +85°C operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with CY8C6244AZI-S4D93, CY8C6247AZI-D54 sacrifices CAN FD and memory for smaller footprint, while STM32WB55RGV trades dual-core determinism and hardware security depth for integrated BLE-but neither matches the combination of CAN FD, USB FS, and ROM-based Secure Boot in a single 80-pin TQFP package.

Availability

CY8C6244AZI-S4D93 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home hubs, medical wearables, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for CY8C6244AZI-S4D93 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and security solutions, with global R&D and manufacturing infrastructure.

The PSoC™ 62 product line targets secure, ultra-low-power IoT endpoints-designed to unify sensing, connectivity, and trusted execution in a single chip for battery-operated and safety-aware edge applications.

FAQ

Does CY8C6244AZI-S4D93 support USB device enumeration without external components?

Yes. The part integrates a full-speed USB 2.0 transceiver with internal termination resistors and voltage regulators. It enumerates as a USB device using only the onboard USB_DP/USB_DM pins and standard USB cable-no external PHY, resistors, or level shifters are required. Firmware must configure the USBFS block and descriptors per the PSoC™ 6 USB Component datasheet.

What is the maximum achievable CAN FD bit rate and how is it configured?

CY8C6244AZI-S4D93 supports CAN FD up to 5 Mbps in the data phase, with programmable bit timing via the CANFD_CBT register. Configuration requires setting nominal and data phase quanta, synchronization jump width, and prescaler values based on the selected clock source (e.g., PLL output). The hardware meets ISO 11898-1 timing requirements for both classic CAN and FD frames.

How does the Secure Boot process validate firmware integrity?

At power-on or reset, the ROM bootloader reads the public key from eFuse and verifies the ECDSA-P256 signature of the flash-resident boot image header. It then computes SHA-256 of the image payload and compares it against the signed hash. Only if both signature and hash match does execution proceed-ensuring immutable chain-of-trust from ROM to application code.

Can the Smart I/O block operate independently during System Deep Sleep?

Yes. The Smart I/O block (6 GPIOs) remains fully functional in System Deep Sleep mode, executing Boolean logic (AND/OR/XOR/NOT) on input states without waking either CPU. Its configuration is retained in dedicated registers powered by the backup domain, enabling autonomous GPIO-level decision-making for wake-event filtering or status encoding.