Infineon Technologies CY8C6244LQI-S4D92

Overview

CY8C6244LQI-S4D92 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 256 KB flash, 128 KB SRAM, integrated CAN FD, USB Full-Speed, QSPI/XIP, and capacitive sensing (CapSense™). It operates from 1.7–3.6 V, achieves 7 µA Deep Sleep current with 64 KB SRAM retention, and supports secure boot via ROM-based root of trust - deployed in battery-powered industrial IoT edge nodes requiring real-time sensor fusion and wireless coexistence.

For engineers reviewing the CY8C6244LQI-S4D92 datasheet, CY8C6244LQI-S4D92 pinout, CY8C6244LQI-S4D92 application, or CY8C6244LQI-S4D92 equivalent, key selection criteria include dual-CPU power/performance trade-offs, on-chip DC-DC quiescent current (<1 µA), CAN FD timing compliance, SMIF XIP encryption capability, and Smart I/O Boolean logic availability during System Deep Sleep.

Technical Context

The device implements a tightly coupled dual-CPU subsystem: the 150-MHz Cortex-M4F handles compute-intensive tasks (e.g., sensor fusion, crypto acceleration) with FPU and MPU, while the 100-MHz Cortex-M0+ manages low-power peripherals and real-time control. Inter-processor communication (IPC) uses hardware semaphores and message passing for deterministic task partitioning.

Its programmable analog subsystem includes two synchronized 12-bit 2-Msps SAR ADCs with Deep Sleep operation, a 12-bit DAC (<2 µs settling), two opamps, and two low-power comparators - all accessible during ultra-low-power modes. The CapSense™ CSD block delivers liquid-tolerant proximity and self/mutual sensing with SmartSense auto-tuning.

Key Specifications

Pinout & Package

This device is housed in an 80-pin TQFP (LQI) package with 62 usable GPIOs, including six Smart I/O pins supporting Boolean logic in Deep Sleep, two overvoltage-tolerant (OVT) inputs, and dedicated pins for CAN FD (CANRX/CANTX), USB D+/D−, and QSPI clock/data lines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core, secure MCU applications.

Compared with CY8C6244LQI-S4D92, CY8C6247LQI-D52 trades CAN FD for expanded memory and dual USB - ideal for feature-rich HMI hubs; STM32WB55RGV replaces dual-core determinism and secure XIP with integrated BLE, simplifying RF design at the expense of industrial bus compatibility and encrypted external code execution.

Availability

CY8C6244LQI-S4D92 is available at Aetrix Electronics and suitable for industrial IoT gateways, medical wearables, and automotive body electronics requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for CY8C6244LQI-S4D92 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global R&D centers and ISO/TS 16949-certified manufacturing.

This part belongs to the PSoC™ 62 product line - designed specifically for secure, ultra-low-power IoT endpoints that require dual-core processing, hardware-accelerated cryptography, and robust capacitive sensing in harsh environments.

FAQ

Does CY8C6244LQI-S4D92 support JTAG debugging?

Yes, it supports SWD and JTAG interfaces via the SWJ-DP debug port. The 32-bit Silicon ID is accessible through this interface, with the most significant digit reflecting the Major Die Revision (1) and the next four digits encoding the part number (E4B0 in hex). Debug access can be permanently disabled via eFuse for production security.

What is the maximum operating frequency of the CAN FD peripheral?

The CAN FD block supports data bit rates up to 5 Mbps and nominal bit rates up to 1 Mbps, compliant with ISO 11898-1:2015. It includes dedicated message RAM, TX/RX FIFOs, and hardware timestamping - all operable in Deep Sleep mode when configured with wakeup-enable.

Can the SMIF interface execute code from external flash while applying AES decryption?

Yes, the Serial Memory Interface (SMIF) supports Execute-In-Place (XIP) with on-the-fly AES-128 decryption using keys stored in protected eFuse or secure flash. The 4 KB instruction cache reduces fetch latency and power consumption during encrypted XIP operation.

How many GPIOs support CapSense™ functionality on this device?

Up to 62 GPIOs are available, and all can be assigned to CapSense™ CSD or CSX sensing channels depending on routing constraints. The CSD block supports up to 61 segments and 8 commons, with hardware-accelerated scanning and SmartSense auto-tuning enabled without CPU intervention.