Infineon Technologies CY8C6244LQQ-S4D92
- Part No.:
- CY8C6244LQQ-S4D92
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
CY8C6244LQQ-S4D92.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 68QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,513
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Product details
Overview
CY8C6244LQQ-S4D92 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 256-KB flash, 128-KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography accelerators. It operates from 1.7 V to 3.6 V, achieves 7 µA Deep Sleep current with 64-KB SRAM retention, and supports XIP from external Quad-SPI Flash at up to 320 Mbps - deployed in secure, battery-powered IoT edge nodes requiring real-time sensor fusion and wireless coexistence.
For engineers reviewing the CY8C6244LQQ-S4D92 datasheet, CY8C6244LQQ-S4D92 pinout, CY8C6244LQQ-S4D92 application, or CY8C6244LQQ-S4D92 equivalent, key selection criteria include dual-CPU power-performance tradeoff, on-chip DC-DC quiescent current (<1 µA), CAN FD timing compliance, and SMIF encryption capability for secure firmware updates.
Technical Context
The device implements a tightly coupled dual-CPU subsystem: the 150-MHz Cortex-M4F handles compute-intensive tasks (e.g., sensor fusion, crypto operations) with FPU and MPU, while the 100-MHz Cortex-M0+ manages low-power peripheral orchestration and real-time control. Inter-processor communication uses hardware IPC channels with doorbell interrupts and shared memory regions.
Its clock architecture integrates an 8-MHz IMO (±2%), 32-kHz ILO, programmable PLL/FLL, and crystal oscillators (16–35 MHz + 32 kHz), enabling dynamic frequency scaling across six power modes. The SMIF block supports on-the-fly AES-128 decryption during XIP execution, with 4-KB cache to reduce active cycles and leakage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F (FPU, MPU) + 100-MHz Cortex-M0+ (MPU) |
| Memory | 256-KB application flash (RWW), 32-KB supervisory flash, 128-KB SRAM with per-bank retention control |
| Power Modes | Six modes including Deep Sleep (7 µA @ 64-KB SRAM retention) and Hibernate (200 nA) |
| SMIF/QSPI | Up to 320 Mbps throughput; supports XIP, on-the-fly AES-128 decryption, 4-KB cache |
| Analog Peripherals | Two 12-bit 2-Msps SAR ADCs (sync sampling, 16-channel sequencer), one 12-bit DAC (<2 µs settling), two LP comparators, two opamps |
| Connectivity | CAN FD controller, USB Full-Speed device interface, six configurable SCBs (SPI/I2C/UART), one Deep Sleep SCB |
| Security | ROM-based Secure Boot, execute-only memory, TRNG, hardware crypto accelerators (AES, SHA, ECC) |
Pinout & Package
This device is packaged in an 80-pin TQFP (LQQ) with 0.5-mm pitch, thermally enhanced for industrial ambient operation. Pin functions are validated per Infineon's CY8C62x4 Datasheet Rev. *O, Section 4 "Pinouts".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO0–VDDIO5 | I/O Power Supply | Independent 1.7–3.6 V domains per port group; enables mixed-voltage interfacing and selective power gating |
| VDDD | Digital Core Supply | 1.1 V or 0.9 V selectable core voltage; directly impacts CPU performance vs. leakage tradeoff |
| VDDA | Analog Supply | Separate 1.7–3.6 V rail for ADC/DAC/Opamp; decoupling critical for <1 LSB INL error |
| XRES | Reset Input | Active-low asynchronous reset; internal pull-up; compatible with external RC or supervisor ICs |
| SWDCK/SWDIO | Debug Interface | 2-pin SWD interface supporting full debug, programming, and trace; accessible in all non-Hibernate modes |
| USB_DP/USB_DM | USB Physical Layer | Differential Full-Speed (12 Mbps) transceiver; requires 1.5-kΩ pull-up on DP for device enumeration |
| CAN_TX/CAN_RX | CAN FD Transceiver Interface | Direct connection to external CAN FD transceiver (e.g., TJA1044); supports ISO 11898-1:2015 data rates up to 5 Mbps |
Key Features
| Feature | Design Value |
|---|---|
| Smart I/O Boolean Engine | 6 GPIOs in dedicated Smart I/O port perform logic operations (AND/OR/XOR) autonomously during Deep Sleep - enables wake-on-pattern without CPU intervention |
| Capacitive Sensing (CSD) | Hardware-accelerated sigma-delta sensing with SmartSense auto-tuning; achieves >80 dB SNR and liquid-tolerant touch detection on up to 61 segments |
| Segment LCD Driver | Drives up to 61 segments × 8 commons; operates fully in System Deep Sleep mode - ideal for ultra-low-power display interfaces |
| Programmable Analog Subsystem | Two independent SAR ADCs with synchronized sampling, result averaging, and Deep Sleep operation - supports simultaneous multi-sensor acquisition with <100 ns skew |
| On-chip DC-DC Buck Converter | Integrated buck regulator with <1 µA quiescent current; eliminates need for external PMIC in space-constrained designs |
Applications
| Industrial Sensor Node | Secure Wireless Gateway |
|---|---|
|
Use Scenario: Battery-powered vibration/temperature/humidity monitoring node in predictive maintenance systems. IC Role / Device Role / Timing Role: Dual-core runtime coordination: M0+ samples sensors via SAR ADCs and manages BLE/Wi-Fi coexistence; M4F runs FFT-based anomaly detection and AES-encrypted packet assembly. Use Value: 7 µA Deep Sleep with 64-KB SRAM retention extends 2-AA battery life to >5 years; on-chip DC-DC eliminates external regulator BOM cost and footprint. |
Use Scenario: Edge gateway aggregating Zigbee, Thread, and BLE devices before forwarding to cloud via TLS-secured MQTT over Wi-Fi. IC Role / Device Role / Timing Role: M4F executes TLS 1.2 handshake and AES-GCM encryption; M0+ handles concurrent radio stack scheduling and CAN FD bus bridging to legacy PLCs. Use Value: Hardware crypto accelerators reduce TLS handshake latency by 65% vs. software-only; ROM Secure Boot prevents unauthorized firmware injection during OTA updates. |
| Medical Wearable | Automotive Body Control Module |
|
Use Scenario: ECG/PPG patch with capacitive touch UI, real-time arrhythmia detection, and medical-grade data logging. IC Role / Device Role / Timing Role: CSD subsystem enables dry-electrode touchless UI; SAR ADCs acquire synchronized analog front-end signals; M4F runs FDA-cleared QRS detection algorithm. Use Value: SmartSense auto-tuning maintains touch accuracy across skin impedance variance (1–100 kΩ); temperature sensor calibration improves ADC offset drift compensation. |
Use Scenario: Door module controlling window lift, mirror fold, seat position, and interior lighting with LIN/CAN FD interconnect. IC Role / Device Role / Timing Role: CAN FD block handles high-speed body bus messaging (5 Mbps); TCPWMs drive motor H-bridges with center-aligned PWM and hardware kill signals. Use Value: Integrated CAN FD PHY interface reduces external component count; 12-bit DAC provides precise LED dimming control with <2 µs settling for flicker-free illumination. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WB55RGV6 | Single Cortex-M4 core + Cortex-M0+ radio controller; no CAN FD; Bluetooth 5.0 LE only; 1 MB flash, 256 KB RAM | Lacks CAN FD and USB FS; optimized for BLE-centric wireless endpoints, not wired-wireless hybrid gateways | Select when BLE coexistence and RF certification priority outweigh wired interface needs |
| NXP LPC55S69JBD100 | Dual Cortex-M33 cores (no M0+); no CAN FD; USB HS host/device; 640 KB flash, 320 KB SRAM; no SMIF/XIP support | Higher compute density but no native CAN FD or low-power SMIF; targets audio/AI inference, not sensor fusion + secure comms | Select when cryptographic acceleration (ARM TrustZone) and DSP extensions are primary; avoid if CAN FD or XIP from external flash required |
Compared with STM32WB55RGV6 and LPC55S69JBD100, CY8C6244LQQ-S4D92 uniquely combines CAN FD, USB FS, SMIF with AES decryption, and sub-µA DC-DC quiescent current - making it the only option for battery-powered industrial gateways needing wired/wireless protocol bridging and secure firmware update capability.
Availability
CY8C6244LQQ-S4D92 is available at Aetrix Electronics and suitable for industrial sensor nodes, secure wireless gateways, medical wearables, and automotive body control modules requiring stable component supply across extended product lifecycles.
Supply support for CY8C6244LQQ-S4D92 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and security solutions, with global manufacturing and R&D infrastructure.
The PSoC™ 62 product line targets ultra-low-power, secure IoT endpoints - integrating dual-core processing, hardware security, and programmable analog/digital blocks to eliminate discrete component dependencies in edge intelligence designs.
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CY8C6244LQQ-S4D92?
The Cortex-M4F core operates at up to 150 MHz, confirmed in the CY8C62x4 Datasheet Rev. *O Section 3.1.1. This frequency is achievable under 1.1-V core supply and ambient temperatures ≤85°C. At 0.9-V core voltage, max frequency reduces to 100 MHz to maintain timing closure and power efficiency.
Does CY8C6244LQQ-S4D92 support external memory execution with hardware encryption?
Yes - the Serial Memory Interface (SMIF) supports Execute-In-Place (XIP) from external Quad-SPI Flash with on-the-fly AES-128 decryption. This is implemented in dedicated hardware, requiring no CPU involvement, and is documented in Section 3.5.5 of the datasheet with throughput up to 320 Mbps in quad mode.
How many GPIOs support overvoltage tolerance, and what is the rating?
Two GPIO pins (P0.0 and P0.1) are overvoltage-tolerant (OVT) to 5.5 V, as specified in Section 6.2.4 of the datasheet. These pins retain functionality when interfaced with 5-V logic or sensors, eliminating level-shifters in mixed-voltage system designs.
Is the CAN FD controller compliant with ISO 11898-1:2015, and what is its maximum bit rate?
Yes - the integrated CAN FD controller complies with ISO 11898-1:2015 and supports data bit rates up to 5 Mbps, as verified in Section 3.5.4 and Table 6-72 of the datasheet. It requires an external CAN FD transceiver (e.g., TJA1044) and supports both classic CAN and FD frames with flexible data-length coding.
CY8C6244LQQ-S4D92 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- CANbus, FIFO, I2C, LINbus, QSPI, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, CapSense, LCD, LVD, POR, PWM, WDT
- Number of I/O:
- 52
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 128K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 10b Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6244LQQ-S4D92 FAQ
1.How can I place an order for CY8C6244LQQ-S4D92 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6244LQQ-S4D92 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6244LQQ-S4D92 reliable?
The price and inventory of CY8C6244LQQ-S4D92 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6244LQQ-S4D92 is usually 5 days.
3.What payment methods are accepted for CY8C6244LQQ-S4D92?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6244LQQ-S4D92 transactions.
Note: Certain payment methods may incur a processing fee.
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CY8C6244LQQ-S4D92 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6244LQQ-S4D92 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6244LQQ-S4D92?
For technical support, including CY8C6244LQQ-S4D92 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6244LQQ-S4D92 requirements.
6.How does Aetrix verify that CY8C6244LQQ-S4D92 is sourced from the original manufacturer or authorized distributors?
All CY8C6244LQQ-S4D92 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6244LQQ-S4D92 meets industry standards.
7.What is the process for return or replacement of CY8C6244LQQ-S4D92?
All CY8C6244LQQ-S4D92 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6244LQQ-S4D92, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6244LQQ-S4D92 part is unused and in its original packaging.
Return procedure for CY8C6244LQQ-S4D92:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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