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Infineon Technologies CY8C6245AZI-S3D02
- Part No.:
- CY8C6245AZI-S3D02
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-LQFP
- Datasheet:
-
CY8C6245AZI-S3D02.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 100TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,623
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Product details
Overview
CY8C6245AZI-S3D02 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 MCU with 512 KB flash, 256 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography accelerator. It operates from 1.7–3.6 V, achieves 7 µA Deep Sleep current with 64 KB SRAM retention, and supports secure boot via ROM-based root of trust - deployed in industrial IoT edge nodes requiring low-power wireless sensor fusion and firmware authenticity.
For engineers reviewing the CY8C6245AZI-S3D02 datasheet, CY8C6245AZI-S3D02 pinout, CY8C6245AZI-S3D02 application, or CY8C6245AZI-S3D02 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip DC-DC quiescent current (<1 µA), QSPI XIP with 4 KB cache, and hardware TRNG + AES/SHA acceleration for OTA update integrity.
Technical Context
This MCU integrates two tightly coupled Arm cores: a 150-MHz Cortex-M4F with FPU and MPU, and a 100-MHz Cortex-M0+ with independent power domain and configurable 0.9 V / 1.1 V operation. Inter-processor communication uses hardware IPC channels with doorbell interrupts and shared memory regions.
The programmable analog subsystem includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and averaging, two deep-sleep-capable comparators, and an on-die temperature sensor. Digital peripherals feature twelve TCPWMs, seven SCBs (six configurable as SPI/I²C/UART, one Deep Sleep SCB), and a dedicated CAN FD controller compliant with ISO 11898-1:2015.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F + 100-MHz Cortex-M0+, each with MPU and independent voltage scaling (0.9 V or 1.1 V) |
| Memory | 512 KB flash (RWW), 256 KB SRAM (programmable retention), 32 KB AUXflash, 32 KB SFlash, 2×8 KB CPU-specific caches |
| Power Efficiency | Deep Sleep: 7 µA with 64 KB SRAM retention; Active slope: 22 µA/MHz (M4 @ 0.9 V), 15 µA/MHz (M0+ @ 0.9 V) |
| Analog Peripherals | 12-bit 2-Msps SAR ADC (16-channel sequencer, result averaging), 2 LP comparators (active in Deep Sleep), integrated temp sensor |
| Communication | CAN FD (ISO 11898-1:2015), USB Full-Speed device, 7 SCBs (6 SPI/I²C/UART + 1 Deep Sleep SCB), QSPI/SMIF with XIP & 4 KB cache |
| Security | ROM-based Secure Boot, hardware crypto accelerator (AES-128/256, SHA-1/256, ECC), TRNG, 8 protection contexts, debug disable |
| Capacitive Sensing | CAPSENSE™ CSD engine with SmartSense auto-tuning, liquid tolerance, and self/mutual sensing support |
Pinout & Package
Package: 100-pin TQFP (14 × 14 mm, 0.5 mm pitch), 64 GPIOs including 2 Smart I/O ports (8 pins), 2 overvoltage-tolerant (OVT) pins, and dedicated JTAG/SWD debug interface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO0–VDDIO3 | I/O Power Supply | Four independent 1.7–3.6 V domains enabling mixed-voltage interface operation and selective I/O shutdown |
| VDDD | Digital Core Supply | Core logic supply (0.9 V or 1.1 V); connects to on-chip DC-DC buck converter output |
| XRES | External Reset Input | Active-low asynchronous reset; internal pull-up; compatible with open-drain or push-pull sources |
| SWDCLK / SWDIO | Debug Interface | Two-pin Serial Wire Debug (SWD) interface supporting programming, real-time trace, and secure debug lock |
| USB_DP / USB_DM | USB Physical Layer | Differential Full-Speed (12 Mbps) USB transceiver pins; require 1.5-kΩ pull-up on DP for device enumeration |
| CAN_TX / CAN_RX | CAN FD Transceiver Interface | Dedicated differential pair for CAN FD controller; supports bit rates up to 5 Mbps with built-in bus-off recovery |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Voltage Core Operation | Runtime-selectable 0.9 V or 1.1 V core voltage per CPU enables dynamic trade-off between performance and sub-µA/MHz efficiency |
| Hardware Crypto Acceleration | Dedicated engine executes AES-128/256 encryption/decryption, SHA-256 hashing, and ECDSA signing in <100 cycles per block |
| Smart I/O Boolean Logic | Two 8-pin Smart I/O ports perform real-time AND/OR/XOR/NOT on GPIO states during Deep Sleep without waking CPUs |
| QSPI XIP with On-the-Fly Encryption | Execute code directly from external quad-SPI flash with hardware AES decryption, eliminating software overhead and memory footprint |
| CAPSENSE™ CSD Engine | Sigma-delta modulator with >100 dB SNR, automatic SmartSense tuning, and immunity to water overlay - validated per IEC 61000-4-6 |
Applications
| Industrial Sensor Node | Secure Wireless Gateway |
|---|---|
|
Use Scenario: Battery-powered vibration/temperature node in predictive maintenance systems with BLE/Wi-Fi coexistence. IC Role / Device Role / Timing Role: Dual-core coordination: M0+ handles CAPSENSE™ and ADC sampling in Deep Sleep; M4 processes FFT and encrypts data pre-transmission. Use Value: 7 µA Deep Sleep with 64 KB SRAM retention extends battery life to >5 years; hardware TRNG ensures unique session keys per OTA update. |
Use Scenario: Edge gateway aggregating Modbus RTU, CAN FD, and Zigbee traffic for cloud upload via TLS-secured MQTT. IC Role / Device Role / Timing Role: M4 runs protocol stacks and TLS; M0+ manages CAN FD frame buffering and hardware crypto offload for certificate validation. Use Value: Integrated CAN FD controller eliminates external transceiver; hardware AES-256 reduces TLS handshake latency by 65% vs. software-only implementation. |
| Medical Wearable Hub | Automotive Body Control Module |
|
Use Scenario: Multi-parameter wearable (ECG, SpO₂, motion) with capacitive touch UI and encrypted local storage. IC Role / Device Role / Timing Role: CAPSENSE™ CSD drives waterproof touch buttons; SAR ADC samples ECG at 2 Msps with 16× hardware averaging; M0+ manages BLE advertising intervals. Use Value: SmartSense auto-calibration maintains button accuracy under sweat/water; 12-bit ADC with sequencer enables synchronized multi-sensor acquisition. |
Use Scenario: Low-power body control unit managing door locks, lighting, and seat position memory with CAN FD diagnostics. IC Role / Device Role / Timing Role: CAN FD block handles UDS diagnostics and firmware updates; on-chip DC-DC powers entire module from 12 V battery with <1 µA quiescent current. Use Value: Deep Sleep current of 7 µA meets automotive "parked mode" requirements; hardware crypto validates signed firmware before flash write. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP LPC55S69 | Single Cortex-M33 core (no M0+ companion), no integrated CAN FD, lower SRAM (256 KB), lacks Smart I/O and CAPSENSE™ | Requires external CAN transceiver; less suited for ultra-low-power capacitive UI or dual-core task partitioning | Prefer when Arm TrustZone security suffices and CAN FD is not required |
| Renesas RA6M5 | Single Cortex-M33 core, 1 MB flash, 384 KB SRAM, CAN FD, but no hardware crypto accelerator or CAPSENSE™ | Lacks on-chip TRNG and dedicated crypto engine - AES must be software-implemented or offloaded to external IC | Choose when higher flash density and Ethernet MAC are prioritized over sub-µA Deep Sleep and capacitive sensing |
Compared with LPC55S69 and RA6M5, CY8C6245AZI-S3D02 uniquely delivers dual-core power efficiency (22 µA/MHz @ 0.9 V), integrated CAN FD + USB + crypto + CAPSENSE™ in a single die, enabling consolidated BOMs for battery-constrained IoT endpoints.
Availability
CY8C6245AZI-S3D02 is available at Aetrix Electronics and suitable for industrial sensor nodes, secure wireless gateways, medical wearables, and automotive body control modules requiring stable component supply across multi-year production cycles.
Supply support for CY8C6245AZI-S3D02 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and security solutions, with global manufacturing and R&D infrastructure.
This device belongs to the PSOC™ 62 product line - engineered specifically for secure, ultra-low-power IoT endpoints requiring dual-core processing, hardware-accelerated cryptography, and integrated analog/digital programmability.
FAQ
What is the maximum operating frequency of each CPU core?
The CY8C6245AZI-S3D02 features a 150-MHz Arm Cortex-M4F core with FPU and memory protection unit, and a 100-MHz Cortex-M0+ core - both rated for full-speed operation across the 1.7–3.6 V supply range and industrial temperature grade (–40°C to +85°C). Frequency scaling is supported via PLL and FLL clock sources.
Does this MCU support secure firmware updates over-the-air (OTA)?
Yes. The device implements ROM-based Secure Boot with hardware hashing (SHA-256), step-wise image authentication, execute-only memory protection, and hardware AES-256/SHA-256 acceleration - enabling verified, encrypted OTA updates without exposing keys or plaintext firmware in RAM or flash.
Can the CAPSENSE™ subsystem operate while the CPU cores are in Deep Sleep mode?
Yes. The CAPSENSE™ CSD engine operates autonomously during Deep Sleep using the 32-kHz ILO clock, with results stored in dedicated registers accessible upon wake-up. SmartSense auto-tuning and baseline tracking continue without CPU intervention, reducing active time by up to 90% in touch-button applications.
Is the CAN FD peripheral compliant with ISO 11898-1:2015?
Yes. The integrated CAN FD controller fully complies with ISO 11898-1:2015, supporting data bit rates up to 5 Mbps, flexible data field lengths (up to 64 bytes), and CRC-17/CRC-21 error detection. It requires only an external CAN transceiver (e.g., Infineon TLE9251) for physical layer interfacing.
CY8C6245AZI-S3D02 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-LQFP
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- FIFO, I2C, IrDA, LINbus, MMC/SD/SDIO, QSPI, SmartCard, SPI, UART/USART, USB
- Peripherals:
- Bluetooth, Brown-out Detect/Reset, Cap Sense, DMA, LCD, LVD, POR, PWM, SmartSense, WDT
- Number of I/O:
- 64
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 10b Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6245AZI-S3D02 FAQ
1.How can I place an order for CY8C6245AZI-S3D02 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6245AZI-S3D02 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6245AZI-S3D02 reliable?
The price and inventory of CY8C6245AZI-S3D02 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6245AZI-S3D02 is usually 5 days.
3.What payment methods are accepted for CY8C6245AZI-S3D02?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6245AZI-S3D02 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6245AZI-S3D02?
CY8C6245AZI-S3D02 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6245AZI-S3D02 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6245AZI-S3D02?
For technical support, including CY8C6245AZI-S3D02 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6245AZI-S3D02 requirements.
6.How does Aetrix verify that CY8C6245AZI-S3D02 is sourced from the original manufacturer or authorized distributors?
All CY8C6245AZI-S3D02 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6245AZI-S3D02 meets industry standards.
7.What is the process for return or replacement of CY8C6245AZI-S3D02?
All CY8C6245AZI-S3D02 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6245AZI-S3D02, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6245AZI-S3D02 part is unused and in its original packaging.
Return procedure for CY8C6245AZI-S3D02:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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