Infineon Technologies CY8C6245AZI-S3D62

Overview

CY8C6245AZI-S3D62 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 512-KB flash, 256-KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography acceleration-designed for secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and wireless connectivity.

For engineers reviewing the CY8C6245AZI-S3D62 datasheet, CY8C6245AZI-S3D62 pinout, CY8C6245AZI-S3D62 application, or CY8C6245AZI-S3D62 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip DC-DC converter (<1 µA quiescent), Deep Sleep current (7 µA w/ 64-KB SRAM retention), and integrated CAPSENSE™ with SmartSense auto-tuning.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles complex signal processing and security tasks while the Cortex-M0+ manages low-power peripheral orchestration and real-time sensor I/O-interconnected via IPC and shared memory with hardware-enforced protection contexts. Both cores operate at independently configurable voltages (0.9 V or 1.1 V) to optimize dynamic power scaling.

Its programmable analog-digital fabric includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and averaging, two Deep Sleep-capable comparators, and a dedicated CAPSENSE™ sigma-delta subsystem supporting mutual/self-capacitive sensing with liquid tolerance-enabling robust touch and proximity interfaces without host CPU intervention.

Key Specifications

Pinout & Package

This device is packaged in a 100-pin TQFP (Thin Quad Flat Package) with 64 GPIOs, including two Smart I/O ports (8 pins total), two overvoltage-tolerant (OVT) pins, and dedicated pins for USB D+/D−, CAN H/L, QSPI, and crystal oscillators.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with STM32WB55RG and RA6M5G, CY8C6245AZI-S3D62 uniquely combines sub-µA/MHz dual-core efficiency, on-die CAPSENSE™ with SmartSense, and CAN FD-making it optimal for battery-powered IoT hubs requiring both rich human interface and industrial bus connectivity.

Availability

CY8C6245AZI-S3D62 is available at Aetrix Electronics and suitable for smart home gateways, industrial predictive maintenance sensors, medical wearables, and automotive cabin controllers requiring stable component supply across multi-year production cycles.

Supply support for CY8C6245AZI-S3D62 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and security solutions-with leadership in silicon carbide, radar, and embedded security IP.

This part belongs to the PSoC™ 62 product line, engineered specifically for secure, ultra-low-power IoT endpoints that demand concurrent real-time processing, rich human interface (touch/LCD), and industrial connectivity (CAN FD/USB).

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6245AZI-S3D62?

The Cortex-M4F core operates at up to 150 MHz, verified in the official Infineon datasheet (002-26168 Rev. *N). This frequency is achievable under 1.1-V core supply with appropriate thermal management and clock configuration using the on-chip PLL or FLL. At 0.9 V, the maximum rated frequency is reduced to maintain timing closure and power integrity.

Does CY8C6245AZI-S3D62 support execute-in-place (XIP) from external flash?

Yes, the device supports XIP via its Quad-SPI/SMIF interface with 4-KB on-die cache, enabling direct code execution from external quad SPI flash at up to 320 Mbps. Hardware-accelerated on-the-fly decryption ensures secure boot and runtime code confidentiality without CPU overhead.

Can the CAPSENSE™ subsystem operate during Deep Sleep mode?

Yes, the CAPSENSE™ CSD block remains fully functional in Deep Sleep mode, allowing capacitive touch or proximity detection without waking the CPU cores. It uses the ultra-low-power 32-kHz ILO clock and draws <1 µA during scanning-verified in the device's electrical specifications section (6.3.5 CSD).

What debug interface does CY8C6245AZI-S3D62 use, and is it accessible after security lockdown?

The device uses SWD (Serial Wire Debug) via the SWJ-DP interface, compatible with standard Arm debug tools. After Secure Boot enforcement and debug disable fuse programming, all debug access-including SWD, JTAG, and SWO-is permanently blocked, preventing firmware extraction or runtime inspection while preserving full functional operation.