Infineon Technologies CY8C6245AZI-S3D72

Overview

CY8C6245AZI-S3D72 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller in 100-TQFP package with 64 GPIOs, 512-KB flash, 256-KB SRAM, and integrated CAN FD, USB FS, QSPI/XIP, and CAPSENSE™. It operates from 1.7–3.6 V, achieves 7 µA Deep Sleep current with 64-KB SRAM retention, and targets secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion and wireless coexistence.

For engineers reviewing the CY8C6245AZI-S3D72 datasheet, CY8C6245AZI-S3D72 pinout, CY8C6245AZI-S3D72 application, or CY8C6245AZI-S3D72 equivalent, this page delivers verified core architecture details, validated low-power operating points, confirmed peripheral integration (CAN FD, USB, SMIF), and exact package-to-pin mapping for schematic capture and PCB layout.

Technical Context

The device implements a tightly coupled dual-CPU subsystem: the 150-MHz Cortex-M4F handles complex signal processing and security-critical tasks with hardware FPU and MPU, while the 100-MHz Cortex-M0+ manages real-time I/O, power state coordination, and peripheral offload. Inter-processor communication uses hardware IPC channels with doorbell interrupts and shared memory regions.

Its system-level timing architecture integrates an 8-MHz IMO (±2%), 32-kHz ILO, programmable PLL/FLL, and fractional clock dividers-enabling independent, jitter-controlled clocks for USB, CAN FD, and ADC sampling without external crystals. The on-chip DC-DC buck converter delivers <1 µA quiescent current and supports dynamic voltage scaling between 0.9 V and 1.1 V per core.

Key Specifications

Pinout & Package

Package: 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch), RoHS-compliant, lead-free, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core, secure MCU applications.

Compared with RP2040 and STM32H743VI, CY8C6245AZI-S3D72 uniquely combines certified secure boot, CAN FD + USB FS + QSPI/XIP in one die, and sub-10 µA Deep Sleep with retained SRAM-enabling single-chip, battery-operated, safety-aware edge nodes without external PMIC or crypto co-processors.

Availability

CY8C6245AZI-S3D72 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart home hubs, medical wearables, and automotive body controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for CY8C6245AZI-S3D72 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global R&D centers and ISO/TS 16949-certified manufacturing.

This device belongs to the PSOC™ 62 product line-designed specifically for secure, ultra-low-power IoT endpoints that require concurrent wireless connectivity, capacitive sensing, and functional safety-aware firmware execution.

FAQ

Does CY8C6245AZI-S3D72 support JTAG debugging in all power modes?

Yes-SWD/JTAG debug access remains available in Active, Sleep, and Deep Sleep modes when enabled in the protection context. Debug port can be permanently disabled via eFuse for production units to prevent unauthorized firmware extraction. The silicon ID is accessible through SWJ interface regardless of debug state.

What is the maximum achievable QSPI XIP throughput and how is encryption overhead managed?

The QSPI interface supports up to 320 Mbps in quad mode. On-the-fly AES-128 decryption occurs in hardware with zero CPU involvement; the 4-KB instruction cache buffers decrypted opcodes, eliminating decryption latency penalties during code fetch. No software driver or key management is required for basic XIP operation.

Can the two CPUs run different real-time operating systems simultaneously?

Yes-the M4 and M0+ cores operate independently with separate memory maps, interrupt vectors, and clock domains. FreeRTOS and Keil RTX have been validated on both cores; inter-core messaging uses dedicated IPC hardware with mailbox registers and doorbell interrupts, ensuring deterministic latency below 100 ns.

How does the CAPSENSE™ CSD subsystem achieve liquid tolerance without firmware intervention?

Liquid tolerance is achieved through hardware-based shield electrode drive, adaptive baseline tracking, and sigma-delta modulation with >100 dB SNR. SmartSense auto-tuning adjusts sensor parameters-including modulation frequency, IDAC range, and sample count-in real time based on environmental feedback, requiring no runtime firmware calibration.