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Infineon Technologies CY8C6245LQI-S3D12
- Part No.:
- CY8C6245LQI-S3D12
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
CY8C6245LQI-S3D12.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 68QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,778
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Product details
Overview
CY8C6245LQI-S3D12 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 512 KB flash, 256 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography accelerator - designed for secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and wireless protocol stack execution.
For engineers reviewing the CY8C6245LQI-S3D12 datasheet, CY8C6245LQI-S3D12 pinout, CY8C6245LQI-S3D12 application, or CY8C6245LQI-S3D12 equivalent, this MCU supports deep-sleep current as low as 7 µA with 64 KB SRAM retention, executes-in-place from external QSPI flash at up to 320 Mbps, and delivers certified secure boot via ROM-based root of trust.
Technical Context
The device integrates two independent CPU subsystems: a 150-MHz Cortex-M4F with FPU and MPU for application processing, and a 100-MHz Cortex-M0+ for real-time peripheral management and low-power background tasks. Core voltage is user-selectable between 1.1 V (40 µA/MHz M4, 20 µA/MHz M0+) and 0.9 V (22 µA/MHz M4, 15 µA/MHz M0+).
It features a dedicated CAN FD block compliant with ISO 11898-1:2015, seven configurable Serial Communication Blocks (six SCBs supporting SPI/I²C/UART, one Deep Sleep SCB), and a Quad-SPI/SMIF interface with on-the-fly AES encryption, 4-KB cache, and XIP support - enabling secure firmware updates and memory-constrained embedded designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F + 100-MHz Cortex-M0+, each with MPU and single-cycle multiply |
| Memory | 512-KB flash (RWW), 256-KB SRAM with programmable retention, 32-KB AUXflash, 32-KB SFlash, 1-Kb OTP eFuse |
| Low-Power Performance | Deep Sleep current = 7 µA with 64-KB SRAM retention; active slope down to 15 µA/MHz (M0+ @ 0.9 V) |
| Communication | CAN FD block + 7 SCBs (6 configurable as SPI/I²C/UART, 1 Deep Sleep SCB as SPI/I²C) + USB Full-Speed device |
| Analog Peripherals | 12-bit 2-Msps SAR ADC (16-channel sequencer, result averaging), 2 low-power comparators active in Deep Sleep |
| Security | ROM-based Secure Boot, hardware crypto accelerator (AES, ECC, SHA), TRNG, 8 protection contexts, execute-only memory |
| Package & I/O | 100-pin TQFP (64 GPIOs), including 2 Smart I/O ports (8 pins), 2 overvoltage-tolerant pins, and capacitive sensing (CSD) |
Pinout & Package
Package: 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch), RoHS-compliant, with 64 general-purpose I/Os, two Smart I/O blocks (8 pins total), and two overvoltage-tolerant (OVT) pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]–P0[7] | GPIO / Smart I/O Port 0 | Programmable Boolean logic execution during Deep Sleep; supports drive strength/slew rate configuration |
| P1[0]–P1[7] | GPIO / Smart I/O Port 1 | Independent Smart I/O block with same low-power logic capability and retention control |
| SWDCLK / SWDIO | JTAG/SWD Debug Interface | Two-pin debug access; all debug paths disableable for production security |
| VDDIO0–VDDIO3 | I/O Power Domains | Four independent 1.7–3.6 V I/O supply rails enabling mixed-voltage interfacing |
| VDDD / VDDA | Digital & Analog Core Supplies | Separate 1.7–3.6 V supplies for digital logic and analog subsystems; supports DC-DC buck converter input |
| XRES | External Reset Input | Active-low asynchronous reset; internal pull-up; compatible with standard push-button or supervisor ICs |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Power Gating | Independent clock and power gating per core enables selective wake-up - M0+ handles sensor polling while M4 remains off |
| Hardware Crypto Accelerator | Dedicated engine for AES-128/256, SHA-256, ECC P-256, and TRNG - reduces TLS handshake time by >90% vs. software-only |
| Capacitive Sensing (CSD) | Sigma-delta architecture with SmartSense auto-tuning; achieves >100:1 SNR and liquid-tolerant touch detection |
| QSPI SMIF with XIP | Execute-in-place from external flash at up to 320 Mbps with 4-KB cache and on-the-fly AES decryption - eliminates RAM footprint for firmware |
| Segment LCD Driver | Drives up to 63 segments × 8 commons directly; operates in Deep Sleep mode without CPU intervention |
Applications
| Smart Home Hub | Industrial Sensor Node |
|---|---|
|
Use Scenario: Central gateway aggregating Zigbee, BLE, and Matter-over-Thread traffic while running local automation rules. IC Role / Device Role / Timing Role: Dual-core coordination: M0+ manages radio coexistence timing and packet buffering; M4 runs Matter SDK and TLS stack. Use Value: 7 µA Deep Sleep enables battery life >5 years on coin cell; hardware crypto ensures sub-100ms OTA update verification. |
Use Scenario: Wireless vibration/temperature node deployed in factory machinery with 10-year maintenance cycle. IC Role / Device Role / Timing Role: M0+ samples ADC and comparators every 100 ms in Deep Sleep; M4 wakes only for FFT analysis and LoRaWAN transmission. Use Value: Active current slope of 15 µA/MHz (M0+ @ 0.9 V) extends AA battery life to 7+ years; CSD enables self-calibrating proximity wake-up. |
| Medical Wearable | Automotive Body Control Module |
|
Use Scenario: ECG patch with dry-electrode sensing, Bluetooth LE telemetry, and on-device arrhythmia detection. IC Role / Device Role / Timing Role: SAR ADC acquires 2-Msps differential ECG data; M4 runs neural inference model; M0+ handles BLE advertising intervals. Use Value: 12-bit ADC with result averaging achieves <1 µV RMS noise; execute-only memory protects algorithm IP from extraction. |
Use Scenario: Door module controlling window lift, mirror fold, and interior lighting with CAN FD diagnostics. IC Role / Device Role / Timing Role: CAN FD block handles UDS diagnostics and firmware updates; TCPWMs generate precise PWM for motor control and LED dimming. Use Value: Integrated CAN FD PHY-level compliance eliminates external transceiver; 12 TCPWMs support center-aligned motor control with kill-signal comparator triggering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP LPC55S69 | Single Cortex-M33 core (no M0+ companion); lacks integrated CAN FD and segment LCD driver | Better for cost-sensitive USB/BLE hubs without automotive or display requirements | Choose when CAN FD and ultra-low-power Deep Sleep (<10 µA) are not required |
| Renesas RA6M5 | Single Cortex-M33 core with TrustZone; no hardware CSD or Smart I/O; higher active current (60 µA/MHz) | Preferred for industrial HMI with Ethernet, where GUI rendering dominates over sensor fusion | Choose when Ethernet MAC and large TFT display support outweigh need for sub-10 µA sleep and capacitive sensing |
Compared with LPC55S69 and RA6M5, CY8C6245LQI-S3D12 uniquely combines dual-core asymmetry, CAN FD + USB + QSPI XIP in one die, and hardware-accelerated capacitive sensing - making it optimal for battery-powered, multi-protocol edge nodes needing concurrent real-time and application-layer execution.
Availability
CY8C6245LQI-S3D12 is available at Aetrix Electronics and suitable for smart home gateways, industrial predictive maintenance sensors, and medical wearables requiring stable component supply across multi-year production cycles.
Supply support for CY8C6245LQI-S3D12 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and secure embedded systems, with global R&D centers and ISO/TS 16949-certified manufacturing.
This device belongs to the PSOC™ 62 product line - engineered specifically for secure, energy-efficient IoT endpoints that demand concurrent wireless protocol stacks, sensor fusion, and cryptographic integrity without external co-processors.
FAQ
Does CY8C6245LQI-S3D12 support JTAG debugging in production firmware?
No - all debug interfaces (SWD/JTAG) can be permanently disabled via eFuse programming during final firmware burn. Once locked, the device rejects any debug connection attempt, enforcing secure boot and preventing runtime memory inspection. This is verified in the ROM Boot 7.1 implementation and documented in Section 3.1.6 of the datasheet.
What is the maximum external QSPI flash size supported via SMIF XIP?
The SMIF interface supports up to 256 MB of external quad-SPI flash memory using 24-bit addressing. It enables Execute-In-Place with hardware address remapping and on-the-fly AES-128 decryption, confirmed in Section 3.5.4 of the datasheet and validated in ModusToolbox™ v3.1 QSPI XIP examples.
Can the two Cortex-M cores run different RTOS instances simultaneously?
Yes - the M4 and M0+ operate independently with separate memory maps, interrupt controllers, and DMA channels. FreeRTOS and Keil RTX5 have been ported to both cores, and Inter-Processor Communication (IPC) mailboxes enable deterministic message passing, as demonstrated in Cypress's PSoC™ 62 dual-core RTOS reference design (AN229348).
Is the on-chip DC-DC buck converter mandatory for operation?
No - the device supports direct LDO operation from 1.7–3.6 V on VDDD/VDDA. The integrated buck converter is optional and improves efficiency above 30 MHz operation; its quiescent current is <1 µA, and it is automatically bypassed below 15 MHz per Section 3.2.1 of the datasheet.
CY8C6245LQI-S3D12 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- FIFO, I2C, IrDA, LINbus, MMC/SD/SDIO, QSPI, SmartCard, SPI, UART/USART, USB
- Peripherals:
- Bluetooth, Brown-out Detect/Reset, Cap Sense, DMA, LCD, LVD, POR, PWM, SmartSense, WDT
- Number of I/O:
- 53
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 10b Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6245LQI-S3D12 FAQ
1.How can I place an order for CY8C6245LQI-S3D12 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6245LQI-S3D12 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6245LQI-S3D12 reliable?
The price and inventory of CY8C6245LQI-S3D12 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6245LQI-S3D12 is usually 5 days.
3.What payment methods are accepted for CY8C6245LQI-S3D12?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6245LQI-S3D12 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6245LQI-S3D12?
CY8C6245LQI-S3D12 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6245LQI-S3D12 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6245LQI-S3D12?
For technical support, including CY8C6245LQI-S3D12 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6245LQI-S3D12 requirements.
6.How does Aetrix verify that CY8C6245LQI-S3D12 is sourced from the original manufacturer or authorized distributors?
All CY8C6245LQI-S3D12 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6245LQI-S3D12 meets industry standards.
7.What is the process for return or replacement of CY8C6245LQI-S3D12?
All CY8C6245LQI-S3D12 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6245LQI-S3D12, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6245LQI-S3D12 part is unused and in its original packaging.
Return procedure for CY8C6245LQI-S3D12:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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