Infineon Technologies CY8C6245LQI-S3D42

Overview

CY8C6245LQI-S3D42 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 512-KB flash, 256-KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography acceleration-designed for secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and wireless connectivity.

For engineers reviewing the CY8C6245LQI-S3D42 datasheet, CY8C6245LQI-S3D42 pinout, CY8C6245LQI-S3D42 application, or CY8C6245LQI-S3D42 equivalent, key selection considerations include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), Deep Sleep current (7 µA w/ 64-KB SRAM retention), QSPI XIP with on-the-fly encryption, and CAN FD + USB coexistence in a single die.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles complex signal processing and security tasks while the Cortex-M0+ manages low-latency peripherals and power-state coordination via IPC and shared memory. Both cores operate at independent voltages (0.9 V or 1.1 V) with dedicated DMA controllers and flash caches.

Its programmable analog-digital fabric includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer, two Deep Sleep-capable comparators, CAPSENSE™ sigma-delta CSD with SmartSense auto-tuning, and a dedicated CAN FD controller compliant with ISO 11898-1:2015 supporting data rates up to 5 Mbps.

Key Specifications

Pinout & Package

This device is housed in a 100-pin TQFP package (14 mm × 14 mm, 0.5 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 total pins) enabling Boolean logic during Deep Sleep.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with LPC55S69 and RA6M5, CY8C6245LQI-S3D42 uniquely delivers concurrent ultra-low-power peripheral autonomy (Smart I/O, LP comparators), integrated CAN FD + USB, and production-ready CAPSENSE™-enabling single-die solutions for battery-powered, sensor-rich, and automotive-connected edge nodes.

Availability

CY8C6245LQI-S3D42 is available at Aetrix Electronics and suitable for smart home gateways, industrial predictive maintenance sensors, medical wearables, and automotive body electronics requiring stable component supply across multi-year production cycles.

Supply support for CY8C6245LQI-S3D42 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power systems, automotive ICs, and secure microcontrollers, with global manufacturing and automotive-grade quality certification (IATF 16949).

This part belongs to the PSOC™ 62 product line-designed specifically for secure, energy-efficient IoT endpoints that demand concurrent wireless connectivity, real-time control, and robust hardware-rooted security in constrained form factors.

FAQ

Does CY8C6245LQI-S3D42 support true hardware-based secure boot with immutable root of trust?

Yes. It features ROM-based Secure Boot that performs cryptographic verification of the first-stage bootloader using hardware-accelerated SHA-256 and ECC-256 before any user code executes. The ROM code is unmodifiable and provides an immutable root of trust, preventing unauthorized firmware injection at power-on.

What is the maximum achievable CAN FD data rate and physical layer compliance for this device?

The integrated CAN FD controller complies fully with ISO 11898-1:2015 and supports bit rates up to 5 Mbps in the data phase. It includes configurable bit timing, automatic retransmission, error confinement, and built-in loopback mode for validation-requiring only an external CAN transceiver for physical layer interfacing.

Can the SAR ADC operate independently during Deep Sleep mode without waking either CPU core?

No-the SAR ADC itself cannot run autonomously in Deep Sleep. However, the device supports ADC-triggered wakeup: a comparator or TCPWM event can initiate conversion upon exit from Deep Sleep, and the result is placed into SRAM before full CPU wake. For continuous low-power sensing, use the two LP comparators, which remain fully operational in Deep Sleep.

Is QSPI XIP supported with on-the-fly decryption, and what encryption standard is used?

Yes. The SMIF block enables Execute-In-Place from external quad SPI flash with hardware-accelerated AES-128 decryption applied transparently to every fetched instruction. Decryption occurs in-line with zero software overhead, and the 4-KB SMIF cache maintains performance while minimizing active flash access time and power.