Infineon Technologies CY8C6245LQI-S3D62
- Part No.:
- CY8C6245LQI-S3D62
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
CY8C6245LQI-S3D62.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 68QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,998
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Product details
Overview
CY8C6245LQI-S3D62 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 512-KB flash, 256-KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography accelerator-designed for secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and wireless protocol stack execution.
For engineers reviewing the CY8C6245LQI-S3D62 datasheet, CY8C6245LQI-S3D62 pinout, CY8C6245LQI-S3D62 application, or CY8C6245LQI-S3D62 equivalent, this MCU delivers verified low-power operation (7 µA Deep Sleep with 64-KB SRAM retention), on-chip DC-DC buck converter (<1 µA quiescent), and programmable analog/digital subsystems enabling rapid sensor fusion and human interface development.
Technical Context
The device implements a tightly coupled dual-CPU architecture: the 150-MHz Cortex-M4F handles complex firmware tasks (e.g., protocol stacks, signal processing) while the 100-MHz Cortex-M0+ manages real-time peripherals and low-power state coordination. Inter-processor communication (IPC) and shared memory enable deterministic task partitioning without bus contention.
Its programmable analog subsystem includes a 12-bit 2-Msps SAR ADC with 16-channel sequencer and hardware averaging, two deep-sleep-capable comparators, and an integrated temperature sensor-all routed through a unified I/O matrix supporting overvoltage-tolerant (OVT) pins and Smart I/O Boolean logic during system Deep Sleep.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F + 100-MHz Cortex-M0+, each with MPU and single-cycle multiply |
| Memory | 512-KB application flash (RWW), 256-KB SRAM with programmable retention granularity, 1-Kb OTP eFuse |
| Low-Power Performance | 7 µA Deep Sleep current with 64-KB SRAM retention; 22 µA/MHz M4 @ 0.9 V core voltage |
| Analog Peripherals | 12-bit 2-Msps SAR ADC (16-channel sequencer, hardware averaging), 2x LP comparators active in Deep Sleep |
| Communication | 7 configurable SCBs (SPI/I²C/UART), 1 Deep Sleep SCB, USB Full-Speed device, CAN FD block, QSPI/SMIF with XIP & encryption |
| Security | ROM-based Secure Boot, hardware crypto accelerator (AES/SHA/RSA/ECDSA), TRNG, 8 protection contexts |
| Capacitive Sensing | CAPSENSE™ CSD subsystem with SmartSense auto-tuning, liquid tolerance, and self/mutual sensing support |
Pinout & Package
This device is packaged in a 100-pin TQFP (14 mm × 14 mm, 0.5-mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and eight Smart I/O pins supporting Boolean operations in Deep Sleep.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]–P0[7] | GPIO / Smart I/O Port 0 | Supports Boolean logic (AND/OR/XOR) in Deep Sleep; configurable drive strength/slew rate |
| P1[0]–P1[7] | GPIO / Smart I/O Port 1 | Same Smart I/O capability as Port 0; enables wake-on-event from ultra-low-power state |
| VBAT | Backup Domain Supply | Powers RTC and 64-byte backup RAM during main power loss; supports coin-cell backup |
| VDDIO0–VDDIO3 | I/O Power Domains | Independent 1.7–3.6-V supplies per port group; enables mixed-voltage interfacing |
| SWDCLK / SWDIO | JTAG/SWD Debug Interface | 2-pin Serial Wire Debug; supports secure debug disable via eFuse lock |
| USB_DP / USB_DM | USB Full-Speed PHY | Differential pair compliant with USB 2.0 FS signaling; internal termination enabled |
| CAN_TX / CAN_RX | CAN FD Transceiver Interface | Direct connection to external CAN transceiver; supports ISO 11898-1 up to 5 Mbps |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Voltage Core Operation | User-selectable 1.1 V or 0.9 V CPU supply enables dynamic trade-off between performance (150 MHz) and ultra-low active current (22 µA/MHz) |
| On-Chip DC-DC Buck Converter | Integrated regulator with <1 µA quiescent current reduces external BOM count and improves battery life in portable IoT nodes |
| Execute-In-Place (XIP) from QSPI | Enables direct code execution from external flash using 4-KB cache, eliminating SRAM footprint for firmware storage |
| Hardware-Accelerated CAPSENSE™ | Dedicated CSD block delivers >100 dB SNR, supports proximity detection through glass/plastic, and auto-calibrates via SmartSense |
| Deep Sleep SCB | One serial block remains operational in Deep Sleep mode, enabling I²C/SPI slave wake-up without CPU intervention |
Applications
| Smart Home Hub | Industrial Sensor Node |
|---|---|
|
Use Scenario: Central gateway aggregating BLE/Zigbee sub-devices while running local decision logic and OTA updates. IC Role / Device Role / Timing Role: Dual-core runtime partitioning: M0+ handles radio MAC timing and interrupt-driven I/O; M4 runs protocol stacks and TLS encryption. Use Value: 7 µA Deep Sleep with 64-KB retained SRAM allows fast wake-to-network-resume (<100 µs), minimizing latency in mesh rejoin sequences. |
Use Scenario: Battery-powered vibration/temperature node deployed in predictive maintenance systems with 10-year field life. IC Role / Device Role / Timing Role: SAR ADC samples accelerometer and thermistor at 1-kSPS; M0+ triggers wake-on-threshold via comparator; M4 processes FFT and compresses data. Use Value: On-chip DC-DC buck and 22 µA/MHz M4 efficiency extend battery life by >3× versus discrete PMIC + MCU solutions. |
| Medical Wearable | Automotive Body Control Module |
|
Use Scenario: ECG patch with capacitive touch UI, motion sensing, and Bluetooth LE telemetry. IC Role / Device Role / Timing Role: CAPSENSE™ CSD drives dry-electrode touch interface; ADC digitizes analog front-end; crypto engine signs biosensor data. Use Value: Smart I/O ports perform button debouncing and LED PWM in Deep Sleep, reducing average system power to <15 µA. |
Use Scenario: Door module managing window lift, mirror fold, and interior lighting with LIN/CAN FD communication. IC Role / Device Role / Timing Role: CAN FD block handles high-speed body bus messaging; TCPWMs generate precise motor control waveforms; OVT pins interface with 12-V switches. Use Value: 64 GPIOs with per-port VDDIO domains allow direct 5-V/12-V peripheral interfacing without level shifters, simplifying PCB layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WB55RGV | Single-core Cortex-M4 + dedicated Cortex-M0+ radio coprocessor; no integrated CAN FD; 256-KB flash | Lacks native CAN FD and hardware CAPSENSE™; optimized for Bluetooth LE + Zigbee coexistence, not automotive or industrial CAN networks | Select when BLE/Zigbee radio integration outweighs need for CAN FD or analog subsystem depth |
| NXP KW45B41Z | ARM Cortex-M0+ only; 512-KB flash but no M4 core; integrated 2.4-GHz radio; no CAN FD or USB | Targeted at simple wireless sensor endpoints-not suitable for compute-intensive edge AI or multi-protocol gateways | Choose for cost-sensitive, radio-centric designs where dual-core processing and peripheral richness are unnecessary |
Compared with STM32WB55RGV and KW45B41Z, CY8C6245LQI-S3D62 uniquely combines CAN FD, USB FS, hardware crypto, and programmable analog/digital fabric in a single die-enabling consolidated BOMs for complex IoT edge controllers without external ASICs or PMICs.
Availability
CY8C6245LQI-S3D62 is available at Aetrix Electronics and suitable for smart home hubs, industrial sensor nodes, medical wearables, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and qualified traceable sourcing.
Supply support for CY8C6245LQI-S3D62 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, security solutions, and embedded controllers-with global manufacturing, qualification, and automotive-grade reliability certification.
This part belongs to the PSoC™ 62 product line, engineered specifically for secure, ultra-low-power IoT endpoints that demand concurrent real-time responsiveness, wireless connectivity, and hardware-enforced trust anchors.
FAQ
What is the maximum operating frequency of each CPU core in CY8C6245LQI-S3D62?
The Cortex-M4F core operates up to 150 MHz with single-cycle multiply and floating-point unit; the Cortex-M0+ core runs at up to 100 MHz with single-cycle multiply. Both include memory protection units (MPUs) and support independent voltage scaling (0.9 V or 1.1 V) to optimize performance versus active current draw.
Does CY8C6245LQI-S3D62 support hardware encryption acceleration?
Yes-it integrates a dedicated cryptography accelerator supporting AES-128/256, SHA-1/224/256, RSA up to 4096-bit, ECC NIST P-256/P-384, and true random number generation (TRNG). All cryptographic operations execute in protected memory space with execute-only permissions enforced by hardware.
Can the SAR ADC operate during Deep Sleep mode?
No-the 12-bit SAR ADC requires active CPU clocking and cannot sample in Deep Sleep. However, two low-power comparators remain fully functional in Deep Sleep and can trigger wake events or drive Smart I/O logic without CPU involvement.
What package type and pin count does CY8C6245LQI-S3D62 use?
CY8C6245LQI-S3D62 uses a 100-pin TQFP package (14 mm × 14 mm, 0.5-mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins, eight Smart I/O pins, and dedicated USB/CAN FD/SMIF interface signals mapped to fixed ballouts per the datasheet pinout diagram.
CY8C6245LQI-S3D62 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, MMC/SD/SDIO, QSPI, SmartCard, SPI, UART/USART, USB
- Peripherals:
- Bluetooth, Brown-out Detect/Reset, Cap Sense, DMA, LCD, LVD, POR, PWM, SmartSense, WDT
- Number of I/O:
- 53
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 10b Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6245LQI-S3D62 FAQ
1.How can I place an order for CY8C6245LQI-S3D62 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6245LQI-S3D62 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6245LQI-S3D62 reliable?
The price and inventory of CY8C6245LQI-S3D62 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6245LQI-S3D62 is usually 5 days.
3.What payment methods are accepted for CY8C6245LQI-S3D62?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6245LQI-S3D62 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6245LQI-S3D62?
CY8C6245LQI-S3D62 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6245LQI-S3D62 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6245LQI-S3D62?
For technical support, including CY8C6245LQI-S3D62 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6245LQI-S3D62 requirements.
6.How does Aetrix verify that CY8C6245LQI-S3D62 is sourced from the original manufacturer or authorized distributors?
All CY8C6245LQI-S3D62 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6245LQI-S3D62 meets industry standards.
7.What is the process for return or replacement of CY8C6245LQI-S3D62?
All CY8C6245LQI-S3D62 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6245LQI-S3D62, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6245LQI-S3D62 part is unused and in its original packaging.
Return procedure for CY8C6245LQI-S3D62:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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