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Infineon Technologies CY8C6245LQI-S3D72
- Part No.:
- CY8C6245LQI-S3D72
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 68-VFQFN Exposed Pad
- Datasheet:
-
CY8C6245LQI-S3D72.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 68QFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,708
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Product details
Overview
CY8C6245LQI-S3D72 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSOC™ 62 microcontroller with 512 KB flash, 256 KB SRAM, integrated CAN FD, USB Full-Speed, and hardware cryptography acceleration-designed for secure, ultra-low-power IoT edge nodes requiring real-time sensor fusion and wireless coexistence.
For engineers reviewing the CY8C6245LQI-S3D72 datasheet, CY8C6245LQI-S3D72 pinout, CY8C6245LQI-S3D72 application, or CY8C6245LQI-S3D72 equivalent, this page delivers verified core architecture details, Deep Sleep current (7 µA), QSPI XIP throughput (320 Mbps), SAR ADC resolution (12-bit, 2-Msps), and Smart I/O Boolean logic capability in system Deep Sleep mode.
Technical Context
The device implements a tightly coupled dual-CPU subsystem: the 150-MHz Cortex-M4F handles complex signal processing and secure boot validation, while the 100-MHz Cortex-M0+ manages low-latency peripheral control and power state transitions. Both cores operate at either 1.1 V (40/20 µA/MHz) or 0.9 V (22/15 µA/MHz) to optimize active power.
Its programmable analog-digital fabric includes a 12-bit SAR ADC with 16-channel sequencer and hardware averaging, two Deep Sleep-capable comparators, and CAPSENSE™ CSD with SmartSense auto-tuning-enabling simultaneous touch sensing and sensor monitoring without waking the main CPU.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm Cortex-M4F + 100-MHz Cortex-M0+, each with MPU and independent DMA controllers |
| Memory | 512-KB flash (RWW), 256-KB SRAM (programmable retention), 1-Kb OTP eFuse for security keys |
| Low-Power Performance | 7 µA Deep Sleep current with 64-KB SRAM retention; on-chip DC-DC buck converter (<1 µA quiescent) |
| Analog Peripherals | 12-bit 2-Msps SAR ADC with differential/single-ended modes, 16-channel sequencer, and hardware result averaging |
| Digital Interfaces | 1× CAN FD, 1× USB Full-Speed device, 7× SCBs (6 configurable as SPI/I²C/UART, 1 Deep Sleep SCB), QSPI/SMIF with 4-KB cache and XIP encryption |
| Security | ROM-based Secure Boot, hardware crypto accelerator (AES-256, ECC, SHA-256, TRNG), 8 protection contexts, debug disable |
| Capacitive Sensing | CAPSENSE™ CSD with >100 dB SNR, liquid-tolerant proximity/self/mutual sensing, SmartSense auto-calibration |
Pinout & Package
This device is packaged in a 100-pin TQFP (14 mm × 14 mm, 0.5 mm pitch) with 64 GPIOs, including two overvoltage-tolerant (OVT) pins and two Smart I/O ports (8 pins total) supporting Boolean logic in Deep Sleep.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P0[0]–P0[7] | Smart I/O Port A | Supports combinational logic (AND/OR/XOR) and latching in Deep Sleep; enables wake-on-pattern detection |
| P1[0]–P1[7] | Smart I/O Port B | Same functionality as Port A; allows autonomous GPIO-level decision-making without CPU intervention |
| USB_DP / USB_DM | USB Full-Speed Interface | Differential pair compliant with USB 2.0 specification; supports device-only operation with internal transceiver |
| CAN_TX / CAN_RX | CAN FD Physical Layer | Direct connection to external CAN transceiver; supports data rates up to 5 Mbps with flexible bit timing |
| QSPI_SCK / QSPI_SS / QSPI_IO0–IO3 | Quad-SPI Memory Interface | Enables Execute-In-Place from external flash with on-the-fly AES decryption and 4-KB cache for latency reduction |
| VDDIO0–VDDIO3 | I/O Power Domains | Four independent 1.7–3.6 V I/O banks support mixed-voltage interfacing and dynamic voltage scaling per bank |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Core Power Gating | Independent voltage/frequency scaling for M4F and M0+ cores enables asymmetric workload partitioning and sub-µA sleep states |
| Hardware Crypto Acceleration | Dedicated engine for AES-256, ECC (NIST P-256), SHA-256, and TRNG eliminates software overhead and side-channel vulnerabilities |
| Deep Sleep SCB | One serial communication block remains active in Deep Sleep, enabling I²C/SPI slave operation without CPU wake-up |
| Segment LCD Driver | Drives up to 63 segments × 8 commons directly from SRAM buffers; operates during Deep Sleep with 32-kHz ILO clock |
| Smart I/O Logic | Configurable Boolean operations on GPIO pins allow hardware-level event filtering and pattern matching before interrupt generation |
Applications
| Smart Home Hub | Industrial Sensor Node |
|---|---|
|
Use Scenario: Central controller aggregating Zigbee, BLE, and sub-GHz wireless sensor data while managing local UI and OTA updates. IC Role / Device Role / Timing Role: Dual-core runtime orchestration: M4F processes encrypted firmware updates and wireless protocol stacks; M0+ handles real-time GPIO-triggered wake events and watchdog supervision. Use Value: 7 µA Deep Sleep with 64-KB SRAM retention extends battery life beyond 5 years on coin cell; QSPI XIP reduces external memory footprint by eliminating need for parallel NOR flash. |
Use Scenario: Battery-powered vibration/temperature node deployed in remote machinery with CAN FD backhaul to PLC. IC Role / Device Role / Timing Role: Real-time sensor acquisition via 12-bit SAR ADC with hardware averaging; CAN FD block schedules deterministic message transmission synchronized to TCPWM-generated timestamps. Use Value: On-chip DC-DC buck converter maintains stable 1.1-V core supply across 2.0–3.6 V battery range; Smart I/O filters false wake events from EMI-coupled transients. |
| Wearable Health Monitor | Secure Access Terminal |
|
Use Scenario: Optical heart-rate and SpO₂ monitor with capacitive touch UI and Bluetooth LE connectivity. IC Role / Device Role / Timing Role: CAPSENSE™ CSD performs liquid-tolerant finger detection and gesture recognition; M0+ drives LED drivers and photodiode amplifiers while M4F runs PPG signal processing algorithms. Use Value: SmartSense auto-tuning adapts baseline tracking to skin tone and moisture; 2-Msps ADC captures high-fidelity PPG waveforms with minimal oversampling overhead. |
Use Scenario: Tamper-resistant door controller using fingerprint authentication, secure key storage, and encrypted audit logging. IC Role / Device Role / Timing Role: ROM-based Secure Boot validates signed firmware images; hardware crypto engine performs AES-256 encryption of log entries stored in protected flash sectors. Use Value: 1-Kb OTP eFuse stores immutable root keys; debug interface permanently disabled post-production to prevent physical extraction of credentials. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| CY8C6247LQI-S3D44 | Same die revision but 320-KB flash, 192-KB SRAM, no CAN FD block; retains USB, QSPI, and crypto engine | Lacks CAN FD interface; suitable for BLE/Wi-Fi gateways where wired fieldbus is unnecessary | Select when CAN FD is not required and lower memory footprint reduces BOM cost without compromising security features |
| STM32WB55RGV | Single Cortex-M4 core (64 MHz), integrated BLE 5.0 radio, 256-KB flash, 64-KB SRAM, no hardware crypto accelerator | Integrated RF eliminates external transceiver but lacks dual-core isolation and dedicated crypto hardware | Prefer for compact BLE-centric designs where RF integration outweighs need for CAN FD or hardware-accelerated ECC |
Compared with CY8C6245LQI-S3D72, the CY8C6247LQI-S3D44 trades CAN FD and memory capacity for cost-sensitive BLE gateway use, while the STM32WB55RGV replaces dual-core determinism and hardware crypto with integrated BLE-but requires software-based security implementation and lacks Deep Sleep SCB autonomy.
Availability
CY8C6245LQI-S3D72 is available at Aetrix Electronics and suitable for industrial sensor nodes, secure access terminals, smart home hubs, and wearable health monitors requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for CY8C6245LQI-S3D72 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global R&D centers and ISO/TS 16949-certified manufacturing.
This part belongs to the PSOC™ 62 product line-designed specifically for ultra-low-power, secure IoT endpoints that demand concurrent wireless connectivity, rich human interface, and hardware-enforced trust anchors.
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CY8C6245LQI-S3D72?
The Cortex-M4F core operates at up to 150 MHz, confirmed in the official Infineon datasheet (002-26168 Rev. *N, Section 3.1.1). This frequency is achievable under 1.1-V core supply with active cooling; at 0.9 V, maximum frequency is reduced to maintain timing closure and power efficiency.
Does CY8C6245LQI-S3D72 support hardware debugging after Secure Boot lockdown?
No-once debug interfaces are permanently disabled via the eFuse-based "debug disable" feature, SWD/JTAG access is irreversibly blocked. This is enforced by ROM-based Secure Boot and documented in the PSOC™ 62 Security Reference Manual (Section 4.2.3).
Can the QSPI interface execute code directly from external flash while applying AES decryption?
Yes-the SMIF block supports Execute-In-Place (XIP) with on-the-fly AES-128 decryption using keys stored in protected flash or OTP. The 4-KB instruction cache improves effective throughput to 320 Mbps while reducing active power during code fetch.
How many GPIOs remain functional in Deep Sleep mode, and what capabilities do they retain?
Up to 64 GPIOs remain accessible in Deep Sleep, including both Smart I/O ports (16 pins total) which retain full Boolean logic and latching capability. Two low-power comparators and one Deep Sleep SCB also remain active, enabling wake-on-I²C address match or comparator threshold crossing without CPU involvement.
CY8C6245LQI-S3D72 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 68-VFQFN Exposed Pad
- Series:
- PSOC™ 6
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, MMC/SD/SDIO, QSPI, SmartCard, SPI, UART/USART, USB
- Peripherals:
- Bluetooth, Brown-out Detect/Reset, Cap Sense, DMA, LCD, LVD, POR, PWM, SmartSense, WDT
- Number of I/O:
- 53
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x12b SAR, 10b Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6245LQI-S3D72 FAQ
1.How can I place an order for CY8C6245LQI-S3D72 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6245LQI-S3D72 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6245LQI-S3D72 reliable?
The price and inventory of CY8C6245LQI-S3D72 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6245LQI-S3D72 is usually 5 days.
3.What payment methods are accepted for CY8C6245LQI-S3D72?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6245LQI-S3D72 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6245LQI-S3D72?
CY8C6245LQI-S3D72 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6245LQI-S3D72 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6245LQI-S3D72?
For technical support, including CY8C6245LQI-S3D72 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6245LQI-S3D72 requirements.
6.How does Aetrix verify that CY8C6245LQI-S3D72 is sourced from the original manufacturer or authorized distributors?
All CY8C6245LQI-S3D72 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6245LQI-S3D72 meets industry standards.
7.What is the process for return or replacement of CY8C6245LQI-S3D72?
All CY8C6245LQI-S3D72 units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6245LQI-S3D72, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6245LQI-S3D72 part is unused and in its original packaging.
Return procedure for CY8C6245LQI-S3D72:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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