Infineon Technologies CY8C6247BZI-D34

Overview

CY8C6247BZI-D34 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSoC™ 62 microcontroller with 1-MB flash, 288-KB SRAM, integrated SMIF QSPI interface, CAPSENSE™ capacitive sensing, and hardware cryptography accelerator. It operates from 1.7 V to 3.6 V, supports Deep Sleep mode at 7 µA with 64-KB SRAM retention, and targets secure, ultra-low-power IoT edge nodes.

For engineers reviewing the CY8C6247BZI-D34 datasheet, CY8C6247BZI-D34 pinout, CY8C6247BZI-D34 application, or CY8C6247BZI-D34 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip SIMO DC-DC converter (<1 µA quiescent), 32 TCPWM blocks, 9 configurable SCBs, and UDB-based programmable logic for protocol offload.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles real-time signal processing and security-critical tasks while the Cortex-M0+ manages low-power peripheral orchestration and sensor aggregation. Inter-processor communication (IPC) and shared memory enable deterministic task partitioning without bus contention.

Its programmable analog subsystem integrates a 12-bit 1-Msps SAR ADC with 16-channel sequencer and averaging, two low-power comparators active in Deep Sleep, and a 12-bit DAC with <2-µs settling time-enabling closed-loop control and sensor conditioning without external components.

Key Specifications

Pinout & Package

Package: 124-ball BGA (9 mm × 9 mm × 1 mm, 0.8-mm pitch). Pinout validated per Infineon datasheet Rev. *Q (2023-12-13), Table 4 "Pin Assignments" and Figure 4-1 "CY8C62x6/62x7 124-BGA Pinout".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with RP2040 and STM32WB55, CY8C6247BZI-D34 uniquely combines dual-core deterministic partitioning, hardware-accelerated security, CAPSENSE™, and sub-10-µA Deep Sleep with SRAM retention-making it optimal for resource-constrained, sensor-rich, and security-critical IoT endpoints.

Availability

CY8C6247BZI-D34 is available at Aetrix Electronics and suitable for smart home sensor hubs, industrial predictive maintenance nodes, wearable health monitors, and secure access control terminals requiring stable component supply and long-term lifecycle support.

Supply support for CY8C6247BZI-D34 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, and secure embedded solutions, with global manufacturing and R&D infrastructure.

The PSoC™ 62 product line delivers programmable, secure, ultra-low-power MCUs purpose-built for intelligent edge devices in IoT, industrial, and consumer applications-integrating analog, digital, and security resources in a single chip.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6247BZI-D34?

The Cortex-M4F core operates at up to 150 MHz, confirmed in the "CPU and Memory Subsystem" section of the official Infineon datasheet Rev. *Q. This frequency is achievable under 1.1-V core supply and ambient temperatures ≤85°C. At 0.9-V core voltage, maximum frequency is reduced to maintain timing closure and power efficiency.

Does CY8C6247BZI-D34 support Execute-In-Place (XIP) from external flash?

Yes, the integrated Serial Memory Interface (SMIF) supports XIP from external quad SPI flash with hardware acceleration, 4-KB cache, and on-the-fly AES-128 decryption. This capability is explicitly documented in Section 3.6.4 of the datasheet and requires proper configuration of SMIF registers and flash memory mapping in the linker script.

How many GPIO pins support overvoltage tolerance (OVT)?

Six GPIO pins are designated as overvoltage-tolerant (OVT), capable of withstanding up to 5.5 V regardless of VDDIO level. These pins are identified in the "Pin Assignments" table (Section 4) of the datasheet as P0[0], P0[1], P12[0], P12[1], P13[0], and P13[1], and are intended for interfacing with legacy 5-V logic or sensors.

Can the CAPSENSE™ subsystem operate during Deep Sleep mode?

Yes, CAPSENSE™ can operate in Deep Sleep mode using the low-power scanning engine and dedicated clock source. The datasheet confirms that self-capacitance scanning remains functional with typical current consumption of ~10 µA per scan, enabling wake-on-touch while maintaining system-level Deep Sleep current at 7 µA with 64-KB SRAM retention.