Infineon Technologies CY8C6247BZI-D44

Overview

CY8C6247BZI-D44 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSoC™ 62 microcontroller with 1-MB flash, 288-KB SRAM, integrated SIMO DC-DC converter, CAPSENSE™, and hardware crypto acceleration-designed for secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and wireless connectivity.

For engineers reviewing the CY8C6247BZI-D44 datasheet, CY8C6247BZI-D44 pinout, CY8C6247BZI-D44 application, or CY8C6247BZI-D44 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), QSPI XIP with on-the-fly encryption, Deep Sleep SCB support, and 100 GPIOs with Smart I/O Boolean logic in low-power states.

Technical Context

The CY8C6247BZI-D44 implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles compute-intensive tasks (e.g., sensor fusion, crypto) while the Cortex-M0+ manages real-time peripherals and low-power state coordination via IPC and shared memory. Its clock system integrates FLL, PLL, and fractional dividers to deliver precise, low-jitter clocks across domains.

Power management leverages six discrete modes-including Deep Sleep (7 µA with 64-KB SRAM retention) and Hibernate-with on-chip SIMO buck converter (<1 µA quiescent current) and backup domain RTC. Analog subsystem includes 12-bit 1-Msps SAR ADC with 16-channel sequencer, two low-power comparators active in Deep Sleep, and CTBm opamps with configurable gain and bandwidth.

Key Specifications

Pinout & Package

Package: 124-ball BGA (9 mm × 9 mm × 1 mm, 0.8-mm pitch). Pinout validated per Infineon datasheet Rev. *Q (2023-12-13), Table 4 "Pinouts" and Package Drawing BZI-D44.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with RP2040 and STM32WB55, CY8C6247BZI-D44 uniquely combines dual asymmetric cores, hardware crypto, CAPSENSE™, and programmable analog/digital logic-enabling secure, sensor-rich, ultra-low-power edge intelligence without external ICs.

Availability

CY8C6247BZI-D44 is available at Aetrix Electronics and suitable for wearable health monitors, smart home sensor hubs, industrial predictive maintenance nodes, and secure access control terminals requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for CY8C6247BZI-D44 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power systems, automotive MCUs, and secure embedded solutions, with global manufacturing and R&D infrastructure.

The PSoC™ 62 product line targets secure, ultra-low-power IoT endpoints-integrating dual-core processing, programmable analog/digital fabric, and hardware-rooted security to eliminate discrete component count in edge AI and human-interface applications.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6247BZI-D44?

The Cortex-M4F core operates at up to 150 MHz, confirmed in the official Infineon datasheet Rev. *Q (2023-12-13), Section 3.1.1. This frequency is achievable under 1.1-V core supply with appropriate thermal management and clock configuration using the on-chip PLL or FLL.

Does CY8C6247BZI-D44 support Execute-In-Place (XIP) from external flash?

Yes, it supports XIP via the QSPI/SMIF interface with hardware-accelerated AES-128 on-the-fly decryption and a dedicated 4-KB cache. The feature is enabled by configuring the SMIF block and setting appropriate memory map attributes in the linker script, as documented in the PSoC™ 6 Technical Reference Manual.

How many GPIO pins support overvoltage tolerance (OVT)?

Six GPIO pins are explicitly designated as overvoltage-tolerant (OVT), capable of withstanding up to 5.5 V regardless of VDDIO supply level. These pins are identified in the "Pinout" section of the datasheet and are assigned to specific port groups (P0[0], P0[1], P12[0]–P12[3]) for robust interfacing with legacy 5-V peripherals.

Is CAPSENSE™ functionality available in Deep Sleep mode?

No-CAPSENSE™ requires active CPU and analog subsystem clocks and is disabled in Deep Sleep. However, the device supports wake-on-touch using dedicated low-power comparators and Smart I/O logic that can detect capacitance changes and trigger CPU wake-up without full subsystem activation.