Infineon Technologies CY8C6247BZI-D54

Overview

CY8C6247BZI-D54 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSoC™ 62 microcontroller with 1-MB flash, 288-KB SRAM, integrated SMIF QSPI interface, CAPSENSE™ capacitive sensing, and hardware cryptography accelerator. It operates from 1.7 V to 3.6 V, supports Deep Sleep mode at 7 µA with 64-KB SRAM retention, and targets secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and sensor processing.

For engineers reviewing the CY8C6247BZI-D54 datasheet, CY8C6247BZI-D54 pinout, CY8C6247BZI-D54 application, or CY8C6247BZI-D54 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), on-chip SIMO DC-DC converter (<1 µA quiescent), 32 TCPWM blocks, 9 configurable SCBs, and 12-bit 1-Msps SAR ADC with 16-channel sequencer.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles compute-intensive tasks (e.g., signal processing, crypto) while the Cortex-M0+ manages low-latency peripherals and system control-interconnected via IPC and shared memory. Both cores operate at independent voltages (0.9 V or 1.1 V) and support asymmetric power gating.

Its programmable analog subsystem integrates a 12-bit SAR ADC with differential input, on-die temperature sensor, two low-power comparators active in Deep Sleep, and two opamps with CTBm configuration. The digital fabric includes twelve UDBs for Verilog or drag-and-drop peripheral implementation, plus Smart I/O for Boolean logic during Deep Sleep.

Key Specifications

Pinout & Package

Package: 124-ball BGA (9 mm × 9 mm × 1 mm, 0.8-mm pitch). Pinout validated per Infineon datasheet Rev. *Q (2023-12-13), Table 4 "Pinouts" and Figure 4-1 "CY8C6247BZI-D54 Pinout (Top View)".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core secure MCU applications.

Compared with LPC55S69-JBD100 and RA6M5, CY8C6247BZI-D54 uniquely combines dual-core asymmetry, on-die SIMO regulation, CAPSENSE™, and Smart I/O-enabling single-chip sensor fusion and UI in space-constrained, battery-operated endpoints without external analog or power components.

Availability

CY8C6247BZI-D54 is available at Aetrix Electronics and suitable for smart home sensor hubs, wearable health monitors, industrial wireless nodes, and secure access control terminals requiring stable component supply across multi-year production cycles.

Supply support for CY8C6247BZI-D54 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, automotive MCUs, and security ICs, with global manufacturing and R&D infrastructure.

The PSoC™ 62 product line delivers programmable, secure, ultra-low-power MCUs purpose-built for intelligent edge devices in IoT, wearables, and industrial automation-integrating analog, digital, and security resources on a single die.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6247BZI-D54?

The Cortex-M4F core operates at up to 150 MHz, confirmed in the datasheet's "CPU and Memory Subsystem" section. This frequency is achievable under 1.1-V core supply with appropriate thermal and voltage margining. At 0.9-V core, the maximum rated frequency is 100 MHz to maintain timing closure and power efficiency.

Does CY8C6247BZI-D54 support external memory execution via QSPI?

Yes-it supports Execute-In-Place (XIP) directly from external quad-SPI flash using the Serial Memory Interface (SMIF), with hardware-accelerated AES encryption/decryption and a dedicated 4-KB cache to reduce latency and power. XIP is enabled via SMIF configuration registers and requires no host CPU intervention during instruction fetch.

How many GPIO pins support overvoltage tolerance (OVT)?

Six GPIO pins are explicitly designated as overvoltage-tolerant (OVT), as specified in Section 6.2.4 "GPIO" of the datasheet. These pins tolerate up to 5.5 V regardless of VDDIO supply level, enabling direct interfacing with legacy 5-V logic or sensors without level shifters.

Can the CAPSENSE™ subsystem operate during Deep Sleep mode?

Yes-CAPSENSE™ can perform low-power scanning in Deep Sleep mode using the dedicated low-power comparators and IDACs. The SmartSense auto-tuning engine remains functional, and results are stored in retained SRAM. Full-resolution scans require waking the M0+ core, but baseline tracking and gesture detection run autonomously.