Infineon Technologies CY8C6247FDI-D52T
- Part No.:
- CY8C6247FDI-D52T
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 80-XFBGA, WLCSP
- Datasheet:
-
CY8C6247FDI-D52T.pdf
- Description:
- IC MCU 32BIT 1MB FLASH 80WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,162
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Product details
Overview
CY8C6247FDI-D52T from Infineon is a dual-core Arm® Cortex®-M4F/M0+ PSoC™ 62 microcontroller with 1-MB flash, 288-KB SRAM, integrated SIMO DC-DC converter, CAPSENSE™, and hardware crypto accelerator-designed for secure, ultra-low-power IoT edge nodes requiring concurrent real-time control and wireless protocol stack execution.
For engineers reviewing the CY8C6247FDI-D52T datasheet, CY8C6247FDI-D52T pinout, CY8C6247FDI-D52T application, or CY8C6247FDI-D52T equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V M4), QSPI XIP with on-the-fly encryption, Deep Sleep current (7 µA w/ 64-KB SRAM retention), and programmable analog/digital subsystems for sensor fusion and human interface.
Technical Context
The device integrates two tightly coupled Arm cores: a 150-MHz Cortex-M4F with FPU and MPU for application processing, and a 100-MHz Cortex-M0+ for real-time control and low-power background tasks. Inter-processor communication (IPC) and shared memory enable deterministic task partitioning between security-critical and latency-sensitive workloads.
Its programmable analog subsystem includes a 12-bit 1-Msps SAR ADC with 16-channel sequencer and result averaging, two low-power comparators active in Deep Sleep, and a 12-bit DAC with <2-µs settling time-enabling simultaneous sensor acquisition, threshold monitoring, and analog output generation without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Cortex-M4F + 100-MHz Cortex-M0+, each with MPU and single-cycle multiply |
| Memory | 1-MB flash (RWW), 288-KB SRAM (with retention control), 1-Kb OTP eFuse |
| Power Efficiency | 7 µA Deep Sleep current with 64-KB SRAM retention; 22 µA/MHz M4 @ 0.9 V core |
| Analog Peripherals | 12-bit 1-Msps SAR ADC (16-channel sequencer, averaging), 2× LP comparators (Deep Sleep active), 12-bit DAC (<2 µs settling) |
| Digital Peripherals | 9 SCBs (configurable as SPI/I²C/UART), 1 USB FS device, 32 TCPWM blocks, 12 UDBs (Verilog-programmable logic) |
| Security | ROM-based Secure Boot, hardware crypto accelerator (AES/SHA/RSA/ECC/TRNG), 8 Protection Contexts |
| Package | 124-BGA (7 mm × 7 mm × 0.8 mm), 0.4-mm pitch, RoHS-compliant |
Pinout & Package
Package: 124-ball BGA (7 mm × 7 mm × 0.8 mm, 0.4-mm pitch), thermally enhanced, lead-free, RoHS-compliant. Pinout validated per Infineon datasheet Rev. *Q (2023-12-13), Table 4 "Pin Assignments" and Figure 4-1 "124-BGA Pinout Diagram".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO0–VDDIO3 | I/O Power Supply | Four independent 1.7–3.6-V I/O domains enabling mixed-voltage interfacing (e.g., 1.8-V sensors + 3.3-V comms) |
| VDDD/VDDA | Digital/Analog Core Supply | Separate 1.7–3.6-V supplies allow analog noise isolation and dynamic voltage scaling for CPU cores |
| XRES | External Reset Input | Active-low asynchronous reset with internal pull-up; supports system-level fault recovery and brown-out detection |
| SWDCK/SWDIO | Debug Interface | 2-pin SWD interface supporting full debug, programming, and trace via standard ARM CoreSight infrastructure |
| QSPI[0:3]/QSCLK/QSSN | Quad SPI Interface | Dedicated high-speed pins for external flash XIP with hardware encryption/decryption and 4-KB cache coherency |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Voltage Scaling | User-selectable 1.1-V or 0.9-V core operation enables dynamic trade-off between performance (150 MHz M4) and ultra-low-power runtime (22 µA/MHz) |
| On-chip SIMO DC-DC | Single-inductor, multi-output buck converter with <1 µA quiescent current reduces external component count and improves battery life in portable IoT nodes |
| CAPSENSE™ with SmartSense | Hardware-accelerated capacitive sensing with automatic tuning delivers >100:1 SNR and liquid-tolerant touch control without firmware calibration overhead |
| Programmable UDB Logic | 12 universal digital blocks (8 macrocells each) implement custom peripherals (e.g., LIN, S/PDIF, PRS) in Verilog or drag-and-drop primitives-reducing FPGA dependency |
| Secure Boot + Crypto Accelerator | ROM-resident boot loader validates signed firmware images; hardware AES-256/SHA-256/ECC-256 accelerates TLS handshake and OTA update integrity verification |
Applications
| Smart Home Sensor Hub | Wearable Health Monitor |
|---|---|
Use Scenario: Aggregating data from multiple environmental and biometric sensors while running BLE stack and local AI inference. IC Role / Device Role / Timing Role: Dual-core orchestrator: M0+ handles BLE radio timing and sensor polling; M4 runs neural network inference and encrypted cloud upload. Use Value: 7 µA Deep Sleep with 64-KB SRAM retention extends coin-cell battery life to >1 year; on-chip crypto enables end-to-end encrypted sensor data without external secure element. | Use Scenario: Continuous ECG/PPG signal acquisition, motion artifact correction, and real-time arrhythmia detection. IC Role / Device Role / Timing Role: Analog front-end controller: SAR ADC samples at 1 Msps with sequencer-driven channel switching; opamps condition signals; TCPWM generates precise LED drive timing for PPG. Use Value: Integrated 12-bit DAC and low-power comparators enable closed-loop analog feedback during Deep Sleep-reducing wake-ups by 60% vs. polling architectures. |
| Industrial Wireless Node | Secure Edge Gateway |
Use Scenario: Battery-powered vibration/temperature monitoring in predictive maintenance systems with LoRaWAN or NB-IoT backhaul. IC Role / Device Role / Timing Role: Low-power host MCU: SIMO DC-DC powers RF transceiver and sensors from single Li-SOCl₂ cell; CAPSENSE™ detects enclosure tampering. Use Value: 22 µA/MHz M4 efficiency allows 10-ms burst processing every 5 minutes while maintaining 10-year battery life; hardware TRNG seeds LoRaWAN join-request keys. | Use Scenario: Local aggregation and policy enforcement for distributed smart metering or building automation endpoints. IC Role / Device Role / Timing Role: Trusted execution environment: Secure Boot verifies firmware; Protection Contexts isolate metering, comms, and UI stacks; crypto engine signs firmware updates. Use Value: Eight hardware-enforced Protection Contexts prevent lateral movement between functional domains-meeting IEC 62443-3-3 SL2 requirements without software hypervisor overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STM32WB55RGV | Single Cortex-M4 core + dedicated Cortex-M0+ radio coprocessor; no integrated SIMO DC-DC; 1-MB flash but only 256-KB SRAM | Optimized for Bluetooth LE + Zigbee coexistence; lacks CAPSENSE™ and programmable analog/digital logic | Select when BLE/Zigbee protocol stack offload is primary requirement and external PMIC acceptable |
| nRF5340 DK | Dual Cortex-M33 cores (app/network); no hardware crypto acceleration for asymmetric algorithms; 1-MB flash, 256-KB RAM, no integrated DC-DC | Focused on multiprotocol wireless SoC use cases; no native QSPI XIP or CAPSENSE™ support | Select for Thread/Matter gateway designs requiring PSA-certified TrustZone but willing to add external power management |
Compared with STM32WB55RGV and nRF5340 DK, CY8C6247FDI-D52T uniquely combines dual-application cores, on-chip SIMO DC-DC, CAPSENSE™, and UDB programmability-enabling single-chip sensor fusion, secure edge processing, and human interface without external analog/digital glue logic.
Availability
CY8C6247FDI-D52T is available at Aetrix Electronics and suitable for smart home sensor hubs, wearable health monitors, industrial wireless nodes, and secure edge gateways requiring stable component supply across multi-year production cycles.
Supply support for CY8C6247FDI-D52T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive MCUs, and secure connectivity solutions, with global R&D and manufacturing infrastructure.
This part belongs to the PSoC™ 62 product line-designed specifically for secure, ultra-low-power IoT endpoints that integrate sensor processing, wireless protocol stacks, and hardware-enforced trust into a single chip.
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CY8C6247FDI-D52T?
The Cortex-M4F core operates at up to 150 MHz, confirmed in the Infineon datasheet Rev. *Q Section 3.1.1. This frequency is achievable under 1.1-V core supply with appropriate thermal management. At 0.9-V core voltage, maximum frequency is reduced to maintain timing closure and power efficiency, though exact derated value depends on process corner and temperature.
Does CY8C6247FDI-D52T support execute-in-place (XIP) from external QSPI flash?
Yes, it supports XIP via the Serial Memory Interface (SMIF) with hardware on-the-fly AES-256 decryption and a dedicated 4-KB cache. The QSPI interface supports single/dual/quad/octal modes with throughput up to 640 Mbps, and XIP operation is fully compatible with Deep Sleep retention modes per datasheet Section 3.6.4.
How many GPIOs are available, and what advanced I/O features does it offer?
CY8C6247FDI-D52T provides up to 100 programmable GPIOs, including six overvoltage-tolerant (OVT) pins and two Smart I/O ports (16 pins total) that perform Boolean logic in Deep Sleep. Each GPIO supports configurable drive strength, slew rate, and 12+ programmable drive modes-including open-drain, high-Z analog, and resistive pull-up/down-validated in datasheet Section 3.7.
Is the CAPSENSE™ subsystem capable of liquid-tolerant operation?
Yes, CAPSENSE™ supports liquid tolerance through hardware-based shield electrode scanning and automatic recalibration via SmartSense. The subsystem achieves >100:1 signal-to-noise ratio and maintains reliable touch detection under water droplets or condensation, as verified in Infineon's CAPSENSE™ Design Guide (AN92239) and confirmed in datasheet Section 3.8.2.
CY8C6247FDI-D52T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 80-XFBGA, WLCSP
- Series:
- PSOC™ 6
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M4/M0
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- I2C, LINbus, QSPI, SPI, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, CapSense, DMA, I2S, LCD, POR, PWM, WDT
- Number of I/O:
- 62
- Program Memory Size:
- 1MB (1M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 32K x 8
- RAM Size:
- 288K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.71V ~ 5.5V
- Data Converters:
- A/D 16x10b, 16x12b SAR; D/A 2x7b, 1x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY8C6247FDI-D52T FAQ
1.How can I place an order for CY8C6247FDI-D52T through Aetrix?
Please submit a Request for Quotation (RFQ) for CY8C6247FDI-D52T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY8C6247FDI-D52T reliable?
The price and inventory of CY8C6247FDI-D52T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY8C6247FDI-D52T is usually 5 days.
3.What payment methods are accepted for CY8C6247FDI-D52T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY8C6247FDI-D52T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY8C6247FDI-D52T?
CY8C6247FDI-D52T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY8C6247FDI-D52T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY8C6247FDI-D52T?
For technical support, including CY8C6247FDI-D52T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY8C6247FDI-D52T requirements.
6.How does Aetrix verify that CY8C6247FDI-D52T is sourced from the original manufacturer or authorized distributors?
All CY8C6247FDI-D52T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY8C6247FDI-D52T meets industry standards.
7.What is the process for return or replacement of CY8C6247FDI-D52T?
All CY8C6247FDI-D52T units undergo pre-shipment inspection (PSI). If there is an issue with CY8C6247FDI-D52T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY8C6247FDI-D52T part is unused and in its original packaging.
Return procedure for CY8C6247FDI-D52T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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