Infineon Technologies CY8C624ALQI-S2D02

Overview

CY8C624ALQI-S2D02 from Infineon is a dual-core PSOC™ 62 microcontroller featuring a 150-MHz Arm® Cortex®-M4F and 100-MHz Cortex®-M0+ CPU, 2048-KB flash, 1024-KB SRAM, and integrated CAPSENSE™, USB FS, QSPI/XIP, and hardware cryptography. It operates from 1.7 V to 3.6 V with deep-sleep current as low as 7 µA (64-KB SRAM retention), targeting secure, ultra-low-power IoT edge nodes.

For engineers reviewing the CY8C624ALQI-S2D02 datasheet, CY8C624ALQI-S2D02 pinout, CY8C624ALQI-S2D02 application, or CY8C624ALQI-S2D02 equivalent, key selection criteria include dual-CPU power efficiency at 0.9 V/1.1 V core voltage, on-chip DC-DC buck converter (<1 µA quiescent), 32 TCPWMs, 13 configurable SCBs, and ROM-based secured boot with eFuse protection.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the M4F handles complex real-time tasks (e.g., sensor fusion, audio processing) while the M0+ manages low-power background operations (e.g., CAPSENSE™ scanning in Deep Sleep). Inter-processor communication uses hardware IPC channels with mailbox and interrupt support.

Clocking is managed via three independent sources: 8-MHz IMO (±2%), 32-kHz ILO, and external crystal oscillators (16–35 MHz + 32 kHz), with two PLLs and an FLL enabling precise frequency synthesis for USB, audio, and ADC sampling - all routed through integer/fractional dividers to 32 programmable peripheral clocks.

Key Specifications

Pinout & Package

This device is packaged in a 100-ball WLCSP (Wafer-Level Chip Scale Package) with 0.4-mm pitch, optimized for space-constrained IoT endpoints. Pin functions are validated per Infineon's official pinout diagram (Document 002-23185 Rev. *S, Page 32).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core, secure MCU applications.

Compared with CY8C6247LQI-D52, this WLCSP variant trades pin count and thermal dissipation for minimal footprint - ideal for size-constrained designs; versus STM32WB55RGV, it delivers superior analog integration and true hardware-enforced security partitioning at the cost of integrated RF.

Availability

CY8C624ALQI-S2D02 is available at Aetrix Electronics and suitable for wearable health monitors, smart home sensor hubs, industrial wireless nodes, and secure access terminals requiring stable component supply across long-lifecycle deployments.

Supply support for CY8C624ALQI-S2D02 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power systems, automotive ICs, and secure microcontrollers, with global manufacturing and R&D infrastructure.

The PSoC™ 62 product line targets secure, battery-operated IoT endpoints - integrating dual-core processing, hardware security, and programmable analog/digital peripherals into a single ultra-low-power SoC architecture.

FAQ

What is the maximum operating frequency of each CPU core in CY8C624ALQI-S2D02?

The Cortex-M4F core runs at up to 150 MHz, and the Cortex-M0+ core operates at up to 100 MHz. Both frequencies are achievable under 1.1-V core supply; at 0.9-V operation, maximum frequencies are reduced per datasheet derating curves (Section 6.2.2), but full 150/100 MHz is supported at 1.1 V with appropriate thermal design.

Does CY8C624ALQI-S2D02 support Execute-In-Place (XIP) from external flash memory?

Yes - the Quad-SPI/SMIF interface supports XIP from external quad-SPI flash with on-the-fly decryption and a dedicated 4-KB cache. This enables direct code execution without loading into internal RAM, reducing SRAM usage and improving power efficiency during firmware updates or large application loads.

How is secure boot implemented on CY8C624ALQI-S2D02?

Secure boot is enforced by ROM-resident code that verifies digital signatures of the boot image using hardware-accelerated SHA-256 and ECDSA. The root public key is fused in OTP eFuse; only images signed with the corresponding private key will execute. Debug interfaces are permanently disabled after secure lock.

Can CAPSENSE™ operate while the main CPUs are in Deep Sleep mode?

Yes - CAPSENSE™ CSD can scan capacitive buttons/sliders autonomously using the low-power M0+ CPU or dedicated hardware sequencer, with results stored in retained SRAM. Smart I/O ports also enable wake-on-touch detection without CPU intervention, achieving sub-10 µA average current in touch-responsive standby.