Infineon Technologies CY8C6336LQI-BLF02

Overview

CY8C6336LQI-BLF02 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ microcontroller with integrated Bluetooth® 5.0 radio, 1-MB flash, 288-KB SRAM, and programmable analog/digital peripherals. It operates from 1.7–3.6 V, achieves 7 µA Deep Sleep current with 64-KB SRAM retention, and supports secure boot, hardware crypto acceleration, and CAPSENSE™ for touch interfaces in battery-powered IoT edge nodes.

For engineers reviewing the CY8C6336LQI-BLF02 datasheet, CY8C6336LQI-BLF02 pinout, CY8C6336LQI-BLF02 application, or CY8C6336LQI-BLF02 equivalent, key selection criteria include Bluetooth LE 5.0 link-layer concurrency (4 connections), dual-voltage core operation (0.9 V / 1.1 V), SIMO buck converter quiescent current (<1 µA), and QSPI XIP with on-the-fly encryption - all validated for industrial sensor hubs and BLE-enabled wearables.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles real-time signal processing and protocol stacks while the Cortex-M0+ manages low-power BLE Link Layer operations and system supervision. Its Bluetooth subsystem includes a 2.4-GHz RF transceiver with –95 dBm RX sensitivity, programmable TX power up to +4 dBm, and hardware-accelerated AES/SHA/TRNG for secure over-the-air updates.

Power management is orchestrated via six hierarchical modes, including Hibernate (1.2 µA), Deep Sleep (7 µA w/64-KB SRAM retention), and Active (40 µA/MHz @ 1.1 V on M4). Clocking combines an 8-MHz IMO (±2%), FLL/PLL frequency synthesis, and crystal oscillator support (16–35 MHz & 32 kHz) for precise timing across BLE advertising, connection, and sleep intervals.

Key Specifications

Pinout & Package

Package: 104-ball Wafer-Level Chip-Scale Package (WLCSP), 3.2 mm × 3.2 mm, 0.4 mm pitch, RoHS-compliant, thermal pad exposed on bottom.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core BLE MCU applications.

Compared with nRF52840 and DA1469x, CY8C6336LQI-BLF02 uniquely integrates programmable analog (SAR ADC, opamps, comparators), digital logic (UDBs, Smart I/O), and dual-voltage core control - enabling single-chip sensor hub + BLE + security without discrete signal conditioning or glue logic.

Availability

CY8C6336LQI-BLF02 is available at Aetrix Electronics and suitable for smart wearables, industrial sensor nodes, BLE mesh lighting controllers, and secure medical peripherals requiring stable component supply, long-term lifecycle support, and qualified automotive-grade traceability.

Supply support for CY8C6336LQI-BLF02 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor leader specializing in power management, sensing, connectivity, and security solutions for automotive, industrial, and IoT markets.

This part belongs to the PSoC™ 63 product line - designed specifically to unify ultra-low-power BLE connectivity, programmable analog/digital hardware, and hardware-enforced security in a single chip for resource-constrained, battery-operated edge devices.

FAQ

What is the maximum supported external QSPI flash density and interface mode for XIP?

CY8C6336LQI-BLF02 supports QSPI XIP from external flash up to 128 MB using single/dual/quad/dual-quad/octal modes. Maximum throughput reaches 640 Mbps in octal mode with 4-KB on-chip cache reducing effective read latency by 40% compared to uncached access - validated with Micron MT25QL series and Winbond W25Q256JW devices.

Does the Bluetooth subsystem support Bluetooth 5.1 Direction Finding features like AoA/AoD?

No. The CY8C6336LQI-BLF02 implements Bluetooth 5.0 LE only and does not include hardware or firmware support for Angle of Arrival (AoA) or Angle of Departure (AoD) features defined in Bluetooth 5.1. Its Link Layer engine supports advertising extensions, 2 Mbps PHY, and periodic advertising but lacks the IQ sampling capability required for direction finding.

How is the 64-byte backup domain powered during Hibernate mode?

The 64-byte backup domain, including the real-time clock (RTC), is powered by the VBACKUP supply pin - which must be connected to a separate 1.2–3.6 V source (e.g., coin cell or supercapacitor). When VBACKUP is present and VDDD is removed, RTC continues running and retains data with typical current draw of 1.2 µA, enabling calendar-aware wake-up after years of storage.

Can Smart I/O™ blocks operate independently while both CPUs are in Deep Sleep?

Yes. Smart I/O™ blocks retain full functionality in Deep Sleep mode without CPU intervention. Each block accepts input from up to eight GPIOs, performs user-defined Boolean logic (AND/OR/XOR/NAND), and drives outputs or triggers interrupts - enabling wake-up on complex pin-state patterns (e.g., "button press + lid open") while consuming only 200 nA per active block.