Infineon Technologies CY8C6347BZI-BLD43

Overview

CY8C6347BZI-BLD43 from Infineon is a dual-core Arm® Cortex®-M4F/M0+ microcontroller with integrated Bluetooth® 5.0 radio, 1-MB flash, 288-KB SRAM, and programmable analog/digital peripherals. It operates from 1.7 V to 3.6 V, achieves 7 µA Deep Sleep current with 64-KB SRAM retention, and supports secure boot, hardware crypto acceleration, and CAPSENSE™ for touch interfaces. Used in battery-powered IoT edge nodes requiring wireless connectivity and low-power sensing.

For engineers reviewing the CY8C6347BZI-BLD43 datasheet, CY8C6347BZI-BLD43 pinout, CY8C6347BZI-BLD43 application, or CY8C6347BZI-BLD43 equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V on M4), Bluetooth LE 5.0 link-layer concurrency (4 connections), QSPI XIP with on-the-fly encryption, and Smart I/O™ Boolean logic in Deep Sleep mode.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles real-time signal processing and security-critical tasks while the Cortex-M0+ manages Bluetooth LE protocol stack and peripheral offload. Both cores share memory-mapped peripherals via a high-bandwidth interconnect and coordinate via IPC and dual DMA controllers (16 channels each).

Its Bluetooth LE subsystem integrates a 2.4-GHz RF transceiver with –95 dBm RX sensitivity, programmable TX output up to +4 dBm, and a dedicated link-layer engine supporting simultaneous master/slave roles and 2 Mbps PHY. The on-chip SIMO buck converter enables sub-1 µA quiescent operation during voltage regulation.

Key Specifications

Pinout & Package

CY8C6347BZI-BLD43 is housed in a 124-ball BGA package (9 mm × 9 mm, 0.5 mm pitch) with an exposed thermal pad. Pin functions are defined per the Infineon PSoC™ 63 pinout specification for the BLD43 variant, supporting USB, QSPI, multiple SCBs, and Bluetooth antenna interface.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core BLE MCU applications.

Compared with nRF52840 and DA1469x, CY8C6347BZI-BLD43 uniquely combines dual-CPU power efficiency, on-die programmable analog/digital logic, and hardware-enforced security - making it optimal for integrated, sensor-rich, field-upgradable IoT endpoints where component count and firmware integrity are critical.

Availability

CY8C6347BZI-BLD43 is available at Aetrix Electronics and suitable for wearable health monitors, smart home sensor hubs, industrial predictive maintenance nodes, and BLE audio remote controls requiring stable component supply across long-lifecycle deployments.

Supply support for CY8C6347BZI-BLD43 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global R&D and manufacturing infrastructure.

CY8C6347BZI-BLD43 belongs to the PSoC™ 63 product line, designed specifically for secure, ultra-low-power IoT endpoints requiring integrated wireless connectivity, programmable analog/digital logic, and hardware-rooted trust.

FAQ

Does CY8C6347BZI-BLD43 support USB device functionality?

Yes. It integrates a full-speed USB 2.0 device interface with on-chip PHY, supporting standard device classes including HID, CDC, and MSC. USB_DP and USB_DM pins are dedicated and require no external transceiver. Enumeration and descriptor handling are supported in ModusToolbox™ middleware.

What is the maximum operating frequency of the Cortex-M4F core?

The Cortex-M4F core operates at up to 150 MHz, confirmed in the datasheet's "CPU and Memory Subsystem" section. Frequency is derived from the PLL or FLL clock sources, and sustained operation requires proper voltage scaling (1.1 V nominal or 0.9 V low-power mode) and thermal management within the BGA package's ratings.

Can the Bluetooth LE subsystem operate independently of the application CPUs?

Yes. The Bluetooth LE subsystem contains a dedicated link-layer engine and digital PHY that run autonomously. The M0+ core typically hosts the host stack, but the link layer can maintain connections, handle advertising, and manage packet scheduling without M4 or M0+ intervention-enabling true low-power background operation.

Is CAPSENSE™ supported in Deep Sleep mode?

No. CAPSENSE™ requires active clocking and analog biasing, so it is disabled in Deep Sleep mode. However, Smart I/O™ and low-power comparators remain functional and can trigger wake-up events (e.g., button press or threshold crossing) that then activate CAPSENSE™ upon wake.