Infineon Technologies CY8C6347FMI-BLD33T

Overview

CY8C6347FMI-BLD33T from Infineon is a dual-core Arm® Cortex®-M4F/M0+ microcontroller with integrated Bluetooth® 5.0 radio, 1-MB flash, 288-KB SRAM, and programmable analog/digital peripherals. It operates at up to 150 MHz (M4) and 100 MHz (M0+), supports 1.7–3.6 V supply, delivers –95 dBm RX sensitivity, and targets secure, ultra-low-power IoT edge nodes requiring wireless connectivity and local processing.

For engineers reviewing the CY8C6347FMI-BLD33T datasheet, CY8C6347FMI-BLD33T pinout, CY8C6347FMI-BLD33T application, or CY8C6347FMI-BLD33T equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V on M4), Bluetooth LE 5.0 link-layer concurrency (4 connections), QSPI XIP with hardware encryption, and CAPSENSE™ liquid-tolerant capacitive sensing capability.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles high-performance tasks (e.g., protocol stack, signal processing) while the Cortex-M0+ manages real-time I/O, BLE link layer, and low-power state coordination. Memory coherency is maintained via inter-processor communication (IPC) channels and shared SRAM with protection contexts.

Its Bluetooth LE subsystem integrates a 2.4-GHz RF transceiver, digital PHY, and dedicated link-layer engine - enabling simultaneous master/slave operation and 2 Mbps data rate without CPU intervention. The on-chip SIMO buck converter (<1 µA quiescent current) and six power modes support sub-µA deep-sleep operation with 64-KB SRAM retention.

Key Specifications

Pinout & Package

CY8C6347FMI-BLD33T is housed in a 104-ball Wafer-Level Chip-Scale Package (WLCSP, M-CSP), measuring 5.2 mm × 5.2 mm with 0.4-mm pitch. This package supports high-density PCB layouts and thermal performance suitable for compact IoT end nodes.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core BLE MCU applications.

Compared with nRF5340 and DA1469x, CY8C6347FMI-BLD33T uniquely combines dual-CPU security partitioning, hardware-accelerated crypto, CAPSENSE™, and QSPI XIP encryption - making it optimal for certified, sensor-rich, field-upgradable IoT devices requiring minimal BOM count.

Availability

CY8C6347FMI-BLD33T is available at Aetrix Electronics and suitable for smart wearable sensor hubs, secure BLE gateway nodes, low-power home automation remotes, and capacitive control panels requiring stable component supply across production lifecycles.

Supply support for CY8C6347FMI-BLD33T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor leader specializing in power systems, automotive MCUs, and secure connectivity solutions, with global manufacturing and R&D infrastructure.

This part belongs to the PSoC™ 63 product line - designed specifically for secure, ultra-low-power IoT endpoints combining wireless connectivity, programmable analog/digital logic, and hardware-enforced trust anchors.

FAQ

What is the maximum operating frequency of each CPU core in CY8C6347FMI-BLD33T?

The Arm Cortex-M4F core operates at up to 150 MHz with single-cycle multiply, floating-point unit, and memory protection unit enabled. The Cortex-M0+ core runs at up to 100 MHz with identical MPU support. Both cores maintain full peripheral access and interrupt latency consistency at rated frequencies, verified across 1.7–3.6 V supply range and industrial temperature grade.

Does CY8C6347FMI-BLD33T support external flash execution with encryption?

Yes. Its Serial Memory Interface (SMIF) supports Execute-In-Place (XIP) from external quad SPI flash with on-the-fly AES-128 decryption. A dedicated 4-KB cache optimizes instruction fetch bandwidth, and hardware key management isolates encryption keys from application firmware using protection contexts.

How many concurrent Bluetooth LE connections does the on-chip radio support?

The integrated Bluetooth LE 5.0 subsystem supports up to four simultaneous connections - two as master and two as slave - managed entirely by the dedicated link-layer engine. Connection parameters (interval, latency, timeout) are configurable per link, and all encryption/decryption occurs in hardware without CPU involvement.

Is CAPSENSE™ functionality available in low-power modes?

Yes. CAPSENSE™ can operate in Deep Sleep mode using the low-power comparators and dedicated scan sequencer. It supports wake-on-touch with sub-µA active current, maintains baseline tracking during sleep, and resumes full-resolution scanning within 20 µs upon wake - all without waking either CPU core.