Infineon Technologies CY8C6347LQI-BLD52T

Overview

CY8C6347LQI-BLD52T from Infineon is a dual-core Arm® Cortex®-M4F/M0+ microcontroller with integrated Bluetooth® 5.0 radio, 1-MB flash, 288-KB SRAM, and programmable analog/digital peripherals. It operates from 1.7–3.6 V, achieves 7 µA Deep Sleep current with 64-KB SRAM retention, and supports secure boot, hardware crypto acceleration, and CAPSENSE™ capacitive sensing. Used in battery-powered IoT edge nodes requiring concurrent processing, wireless connectivity, and low-power sensor interfacing.

For engineers reviewing the CY8C6347LQI-BLD52T datasheet, CY8C6347LQI-BLD52T pinout, CY8C6347LQI-BLD52T application, or CY8C6347LQI-BLD52T equivalent, key selection criteria include dual-CPU power efficiency (22 µA/MHz @ 0.9 V on M4), Bluetooth LE link-layer concurrency (4 simultaneous connections), QSPI XIP with on-the-fly encryption, and Smart I/O™ Boolean logic in Deep Sleep.

Technical Context

The device implements a tightly coupled dual-CPU subsystem where the Cortex-M4F handles real-time signal processing and security-critical tasks while the Cortex-M0+ manages Bluetooth LE protocol stack and peripheral offload. Memory coherency is maintained via shared SRAM and IPC messaging with hardware semaphore support.

Its Bluetooth LE subsystem integrates a 2.4-GHz RF transceiver with –95 dBm RX sensitivity, programmable TX output up to +4 dBm, and a dedicated link-layer engine supporting master/slave roles and 2 Mbps PHY. The on-chip SIMO buck converter enables sub-1 µA quiescent operation in Deep Sleep mode with backup domain retention.

Key Specifications

Pinout & Package

This device is packaged in a 104-ball Wafer-Level Chip-Scale Package (WLCSP) with 0.4-mm pitch, marked "LQI" per Infineon's package code nomenclature. Pin functions are defined per the CY8C6347LQI-BLD52T-specific pinout diagram in Section 4 of datasheet 002-18787 Rev. *R.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-core BLE MCU applications.

Compared with nRF52840-QIAA and DA1469x, CY8C6347LQI-BLD52T uniquely combines dual-CPU deterministic partitioning, hardware-accelerated full crypto suite, and field-programmable analog/digital resources-enabling single-chip implementation of complex, secure, sensor-rich BLE edge nodes without external components.

Availability

CY8C6347LQI-BLD52T is available at Aetrix Electronics and suitable for smart home sensor hubs, wireless medical wearables, industrial predictive maintenance nodes, and BLE-enabled asset trackers requiring stable component supply across design-in, prototyping, and production ramp phases.

Supply support for CY8C6347LQI-BLD52T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive ICs, security solutions, and embedded controllers, with global manufacturing and R&D infrastructure.

CY8C6347LQI-BLD52T belongs to the PSoC™ 63 product line, designed specifically for secure, ultra-low-power IoT endpoints that integrate wireless connectivity, sensor processing, and human interface functions in a single chip.

FAQ

What is the maximum operating frequency of the Cortex-M4F core in CY8C6347LQI-BLD52T?

The Cortex-M4F core operates at up to 150 MHz, verified by the device's internal PLL configuration and electrical specifications in Section 6.2.2 of datasheet 002-18787 Rev. *R. This frequency is achievable with the 1.1-V core supply and appropriate clock source (e.g., IMO × PLL). At 0.9-V core voltage, maximum frequency is reduced to maintain timing closure and power integrity.

Does CY8C6347LQI-BLD52T support external QSPI flash execution with hardware encryption?

Yes. The Serial Memory Interface (SMIF) supports Execute-In-Place (XIP) from external quad SPI flash with on-the-fly AES-128 decryption enabled via dedicated hardware cipher engine. Decryption keys are stored in protected flash or eFuse, and the 4-KB SMIF cache improves instruction fetch efficiency during XIP operation.

How many simultaneous Bluetooth LE connections does the on-chip radio support?

The integrated Bluetooth LE subsystem supports up to four simultaneous connections-either as master, slave, or mixed role-as confirmed by the Link Layer engine specification in Section 3.3 of the datasheet. Connection concurrency is managed entirely in hardware without CPU intervention, preserving M0+ cycles for application tasks.

Is CAPSENSE™ tuning fully automated in CY8C6347LQI-BLD52T?

Yes. CAPSENSE™ SmartSense provides fully automatic hardware tuning of IDAC, scan resolution, and averaging settings during initialization and runtime. It dynamically adapts to environmental changes (e.g., moisture, temperature drift) without host CPU involvement, delivering consistent SNR >100:1 across operating conditions.