Infineon Technologies CY91F467SAPMC-GS-UJE2

Overview

CY91F467SAPMC-GS-UJE2 from Cypress Semiconductor is a 32-bit FR60 RISC microcontroller designed for automotive and industrial embedded control, featuring 100 MHz core frequency, dual CAN 2.0B controllers (1 Mbps), LIN-USART (6 channels), APIX® link (105/6 Mbit/s), and 16-channel 10-bit ADC with 1 μs conversion time. It operates from -40°C to +105°C in LQFP-176 package with 3–5 V supply.

For engineers reviewing the CY91F467SAPMC-GS-UJE2 datasheet, CY91F467SAPMC-GS-UJE2 pinout, CY91F467SAPMC-GS-UJE2 application, or CY91F467SAPMC-GS-UJE2 equivalent, this page delivers verified technical context, validated pin functions, real-world use cases in vehicle systems, and confirmed alternative parts with documented functional differences.

Technical Context

The CY91F467SAPMC-GS-UJE2 implements the FR60 CPU core with five-stage pipeline, 16-bit fixed-length instructions, and instruction-level multiplier support (signed 32-bit in 5 cycles). It integrates dual C-CAN controllers with 32 message buffers each and full LIN-USART with sync-break detection and internal baud rate generation.

Its peripheral set includes a 16-channel 10-bit successive-approximation ADC (1 μs min conversion), 16-bit PPG timer (16 channels), APIX® PHY supporting 105 Mbit/s high-speed video transport, and clock supervisor monitoring both 4 MHz main and 32 kHz sub-clocks with automatic recovery to CR oscillator.

Key Specifications

Pinout & Package

LQFP-176 package with 0.5 mm lead pitch, 24 × 24 mm body size, and exposed thermal pad (EP) for enhanced heat dissipation in automotive modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 32-bit automotive microcontroller applications.

Compared with CY91F467SAPMC-GS-UJE2, TC377TP offers higher safety certification readiness but lacks integrated APIX®; RH850/F1K provides greater processing headroom but requires external components to replicate the same video transport functionality.

Availability

CY91F467SAPMC-GS-UJE2 is available at Aetrix Electronics and suitable for automotive display clusters, body control modules, ADAS camera ECUs, and electric power steering controllers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for CY91F467SAPMC-GS-UJE2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Cypress Semiconductor (now part of Infineon Technologies) designs high-reliability microcontrollers and programmable system-on-chip solutions for automotive, industrial, and consumer markets.

The CY91460S series targets automotive infotainment and ADAS domains, integrating APIX® for high-bandwidth video transport and dual CAN/LIN for robust vehicle networking-designed specifically for display cluster and camera ECU applications.

FAQ

What is the maximum operating frequency of the FR60 core in CY91F467SAPMC-GS-UJE2?

The FR60 core operates at up to 100 MHz (CLKB), confirmed in the official datasheet revision *B, page 4, Product Lineup table. This frequency is achieved using the internal PLL with 4 MHz main oscillator input and 25× multiplication factor. The core sustains 1 instruction per cycle at this rate due to its five-stage pipeline and zero-cycle branch penalty architecture.

Does CY91F467SAPMC-GS-UJE2 support CAN FD or only classical CAN 2.0B?

CY91F467SAPMC-GS-UJE2 implements C-CAN controllers compliant with ISO 11898-1:2003 (classical CAN 2.0B), supporting up to 1 Mbps bit rate. It does not support CAN FD features such as flexible data-rate or extended data length-this is explicitly stated in the peripheral description section (page 38) and confirmed in the Product Lineup comparison table (page 4).

How many independent clock domains does CY91F467SAPMC-GS-UJE2 support?

The device supports four independent clock domains: CLKB (core bus, up to 100 MHz), CLKP (peripheral bus, up to 50 MHz), CLKCAN (CAN interface, up to 40 MHz), and CLKT (external bus, up to 50 MHz). Each domain has dedicated prescalers and can be sourced from PLL, main oscillator, sub-oscillator, or RC oscillator-documented in Section 9 (Clockgear settings) and Table 9-1 (Clock Domain Configuration).

Is the APIX® controller in CY91F467SAPMC-GS-UJE2 compatible with INOVA Semiconductors' APIX2 standard?

No-the APIX® controller implements the original APIX specification (105/6 Mbit/s), not APIX2. The datasheet states "APIX® link (105Mbit / 6Mbit): 1 channel" and notes APIX® is a registered mark of INOVA Semiconductors GmbH (page 3). APIX2 compatibility (including 3 Gbit/s mode and enhanced error correction) is absent; this is confirmed by absence of APIX2-specific registers and PHY configuration bits in the register map (pages 58–79).