Infineon Technologies CY95F633KPMC-G-SNE2
- Part No.:
- CY95F633KPMC-G-SNE2
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 32-LQFP
- Datasheet:
-
CY95F633KPMC-G-SNE2.pdf
- Description:
- IC MCU 8BIT 12KB FLASH 32LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
CY95F633KPMC-G-SNE2 from Infineon Technologies (formerly Cypress) is an 8-bit Flash microcontroller based on the F2MC-8FX CPU core, featuring 12 KB on-chip Flash, 512 bytes RAM, 29 I/O ports (25 CMOS + 4 N-ch open-drain), and integrated LIN-UART, I²C, UART/SIO, 8/10-bit ADC (8 channels), and multi-pulse generator for DC motor control. It operates up to 16.25 MHz machine clock and supports four low-power standby modes.
For engineers reviewing the CY95F633KPMC-G-SNE2 datasheet, CY95F633KPMC-G-SNE2 pinout, CY95F633KPMC-G-SNE2 application, or CY95F633KPMC-G-SNE2 equivalent, key selection criteria include its LIN-UART capability, dual-bank Flash for concurrent read/program, on-chip debug via 1-wire serial interface, and built-in low-voltage detection reset - all critical for automotive body electronics and industrial motor control designs.
Technical Context
The device implements the F2MC-8FX CPU core with 136 basic instructions, 1–3 byte instruction length, and 61.5 ns minimum instruction execution time at 16.25 MHz. It integrates a clock supervisor counter that monitors both main and subclock oscillation stability.
Its memory architecture includes dual-operation Flash (simultaneous read/erase in separate banks), hardware/software watchdog timers, and a dedicated LIN-UART channel supporting both master and slave roles with full-duplex double buffering and programmable baud rates via reload timer.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | F2MC-8FX 8-bit core with multiplication/division, 16-bit arithmetic, and bit manipulation instructions |
| Flash Memory | 12 KB dual-bank Flash enabling concurrent program/erase and read operations |
| RAM | 512 bytes of on-chip SRAM for data and stack storage |
| ADC | 8-channel 8/10-bit successive approximation ADC with selectable resolution |
| Timers | Two 8/16-bit composite timers, three 8/16-bit PPG channels, one 16-bit PPG timer, and one 16-bit reload timer |
| Communication | One LIN-UART (master/slave), one I²C bus interface, and one UART/SIO with full-duplex double buffer |
| Power Management | Four standby modes (Stop, Sleep, Watch, Time-base timer) with normal/deep options and built-in low-voltage detection reset |
Pinout & Package
This device is packaged in a 32-pin LQFP (LQB032) with 0.8 mm pitch, exposing VCC, VSS, reset, clock inputs (X0/X1), debug (DBG), LIN-UART (SIN/SOT/UCK0), I²C (SDA/SCL), ADC inputs (AN00–AN07), PWM outputs (PPG00–PPG21), and 29 configurable I/Os including 4 N-ch open-drain pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00/INT00/AN00/CMP0_P | General-purpose I/O / External interrupt 0 / ADC input 0 / Comparator positive input | Multi-function pin supporting analog sensing, digital I/O, and interrupt triggering |
| P01/INT01/AN01/CMP0_N | General-purpose I/O / External interrupt 1 / ADC input 1 / Comparator negative input | Enables differential analog measurement and edge-triggered wake-up from standby |
| P04/INT04/AN04/SIN/EC0 | General-purpose I/O / External interrupt 4 / ADC input 4 / LIN-UART receive / External clock 0 | Shared LIN physical layer input and ADC channel for sensor interface consolidation |
| P03/INT03/AN03/SOT | General-purpose I/O / External interrupt 3 / ADC input 3 / LIN-UART transmit | Dedicated LIN bus output with slew-rate control for EMC-compliant signaling |
| P12/DBG/EC0 | Debug interface / External clock 0 | Single-wire debug port for programming and real-time trace without dedicated JTAG pins |
| P60/INT08/SDA/DTTI | External interrupt 8 / I²C data line / Data transfer trigger input | Enables I²C slave communication and synchronous event capture from external peripherals |
| P61/INT09/SCL/TI1 | External interrupt 9 / I²C clock line / Timer input 1 | Supports I²C master clock generation and external pulse counting for speed feedback |
| PF2/RST | Reset input | Active-low hardware reset with internal pull-up; accepts external debounced signal or power-on reset assertion |
Key Features
| Feature | Design Value |
|---|---|
| LIN-UART with master/slave support | Enables direct integration into LIN cluster networks without external transceiver for node-level control |
| Dual-bank Flash memory | Allows firmware updates in-field while maintaining real-time operation via background bank switching |
| Multi-pulse generator (MPG) | Provides hardware-accelerated 3-phase DC motor commutation sequencing with waveform buffer and compare-clear timing |
| On-chip low-voltage detection | Four selectable voltage thresholds (2.7 V, 3.0 V, 3.3 V, 3.6 V) with independent release hysteresis for robust brown-out recovery |
| 1-wire on-chip debug | Reduces PCB footprint and BOM cost by eliminating dedicated debug headers while supporting flash programming and runtime inspection |
Applications
| Automotive Body Control Module | Industrial DC Motor Controller |
|---|---|
|
Use Scenario: Centralized control of door locks, window lifts, and mirror adjustment in 12 V vehicle electrical systems. IC Role / Device Role / Timing Role: Primary MCU managing LIN slave nodes, analog sensor inputs (potentiometers, current sense), and PWM-driven motor drivers. Use Value: Integrated LIN-UART eliminates external transceiver; MPG hardware reduces CPU load during commutation; low-voltage detection ensures safe shutdown during battery sag. |
Use Scenario: Closed-loop speed and position control of brushed DC motors in HVAC blowers and conveyor systems. IC Role / Device Role / Timing Role: Real-time motor controller executing commutation logic, reading hall-effect sensors via INT pins, and generating synchronized PWM outputs. Use Value: Dedicated MPG with waveform sequencer enables precise timing of 6-step commutation; 16-bit PPG timers deliver <1 µs jitter for stable RPM regulation. |
| Smart Appliance Power Board | Industrial Sensor Node Gateway |
|
Use Scenario: Main control unit in washing machine or dishwasher power boards managing heater, pump, and valve actuation. IC Role / Device Role / Timing Role: Safety-critical MCU monitoring thermistors (ADC), driving TRIACs via opto-isolated outputs, and logging fault events to Flash. Use Value: Dual-bank Flash allows over-the-air update of safety firmware without interrupting appliance cycle; hardware watchdog prevents runaway code during high-noise EMI conditions. |
Use Scenario: Edge node aggregating temperature, humidity, and vibration data from analog and digital sensors for IIoT reporting. IC Role / Device Role / Timing Role: Low-power coordinator sampling sensors via ADC and I²C, buffering data in RAM, and transmitting via UART to gateway MCU. Use Value: Deep standby mode draws <1 µA; wake-up on external interrupt (e.g., motion sensor) enables event-driven sampling; I²C wake-up function reduces polling overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| RL78/G13 R5F100LEAFP#30 | 16-bit RL78 core, 32 KB Flash, no native LIN-UART (requires software stack), lower max clock (24 MHz CPU, but 8 MHz peripheral bus) | Better suited for general-purpose industrial control where LIN is not required; lacks hardware MPG for motor control | Select if migrating to Renesas ecosystem with need for larger Flash and lower active current, but accept LIN software overhead |
| STM8AF6266TCY | 8-bit STM8 core, 32 KB Flash, automotive-grade AEC-Q100, integrated LINPHY, no dual-bank Flash or MPG | Designed for automotive under-hood use with extended temperature range (−40°C to 150°C); lacks hardware motor control acceleration | Select for AEC-Q100 compliance and certified LINPHY, but expect higher firmware effort for motor timing-critical functions |
Compared with RL78/G13 and STM8AF6266TCY, the CY95F633KPMC-G-SNE2 uniquely combines LIN-UART hardware, multi-pulse generator, and dual-bank Flash in a single 8-bit MCU - delivering lower system-level latency for motor control and faster field updates without external memory.
Availability
CY95F633KPMC-G-SNE2 is available at Aetrix Electronics and suitable for automotive body electronics, industrial motor drives, smart appliance power boards, and IIoT sensor gateways requiring stable component supply across long production lifecycles.
Supply support for CY95F633KPMC-G-SNE2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies acquired Cypress Semiconductor in 2020 and maintains the CY95630H series as part of its industrial and automotive microcontroller portfolio, emphasizing reliability, longevity, and functional safety readiness.
This device belongs to the CY95630H family of general-purpose 8-bit MCUs designed specifically for cost-sensitive, low-power embedded applications requiring LIN communication, analog sensing, and motor control - especially in automotive body and industrial automation domains.
FAQ
Does CY95F633KPMC-G-SNE2 support LIN 2.2 protocol natively?
Yes - the integrated LIN-UART peripheral supports LIN 2.2 frame formatting, checksum calculation (classic/enhanced), automatic sync-break detection, and configurable baud rates via reload timer. It operates as both master and slave without external protocol stack firmware, reducing CPU overhead and latency in automotive network nodes.
What is the maximum operating frequency of the main oscillator?
The main oscillator supports up to 16.25 MHz crystal or ceramic resonator input, yielding a maximum machine clock frequency of 8.125 MHz in main oscillation mode. When using external clock input, the device accepts up to 32.5 MHz, resulting in a maximum machine clock of 16.25 MHz - confirmed in Section 18.4 AC Characteristics of datasheet 002-04627 Rev. *G.
How many I/O pins support N-ch open-drain configuration?
CY95F633KPMC-G-SNE2 provides exactly four N-ch open-drain I/O pins: P00, P01, P02, and P03 - as specified in the "Product Line-up" table on page 3 of datasheet 002-04627 Rev. *G for the "K" variant. These pins are rated for 20 mA sink current and support wired-AND logic and level-shifting interfaces.
Is on-chip debug supported over standard SWD or JTAG?
No - debugging uses a proprietary 1-wire serial interface (DBG pin, P12) with asynchronous serial programming. It does not support SWD or JTAG. The interface requires only VCC, VSS, and DBG connection to Cypress/Infineon evaluation tools like the MiniProg3, enabling flash programming and real-time register inspection without additional pins or protocols.
CY95F633KPMC-G-SNE2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 32-LQFP
- Series:
- F²MC-8FX MB95630H
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- F²MC-8FX
- Core Size:
- 8-Bit
- Speed:
- 16MHz
- Connectivity:
- I2C, LINbus, SIO, UART/USART
- Peripherals:
- LVD, POR, PWM, WDT
- Number of I/O:
- 29
- Program Memory Size:
- 12KB (12K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512 x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 5.5V
- Data Converters:
- A/D 8x8/10b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CY95F633KPMC-G-SNE2 FAQ
1.How can I place an order for CY95F633KPMC-G-SNE2 through Aetrix?
Please submit a Request for Quotation (RFQ) for CY95F633KPMC-G-SNE2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CY95F633KPMC-G-SNE2 reliable?
The price and inventory of CY95F633KPMC-G-SNE2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CY95F633KPMC-G-SNE2 is usually 5 days.
3.What payment methods are accepted for CY95F633KPMC-G-SNE2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CY95F633KPMC-G-SNE2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CY95F633KPMC-G-SNE2?
CY95F633KPMC-G-SNE2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CY95F633KPMC-G-SNE2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CY95F633KPMC-G-SNE2?
For technical support, including CY95F633KPMC-G-SNE2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CY95F633KPMC-G-SNE2 requirements.
6.How does Aetrix verify that CY95F633KPMC-G-SNE2 is sourced from the original manufacturer or authorized distributors?
All CY95F633KPMC-G-SNE2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CY95F633KPMC-G-SNE2 meets industry standards.
7.What is the process for return or replacement of CY95F633KPMC-G-SNE2?
All CY95F633KPMC-G-SNE2 units undergo pre-shipment inspection (PSI). If there is an issue with CY95F633KPMC-G-SNE2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CY95F633KPMC-G-SNE2 part is unused and in its original packaging.
Return procedure for CY95F633KPMC-G-SNE2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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