Infineon Technologies CYB06445LQI-S3D42

Overview

CYB06445LQI-S3D42 from Infineon Technologies (formerly Cypress) is a PSoC 64 "Secure Boot" MCU featuring dual Arm Cortex-M4F (150 MHz) and Cortex-M0+ (100 MHz) CPUs, 384 KB application flash, 176 KB SRAM, hardware-based root-of-trust, and immutable secure boot with ECC signature validation. It targets IoT edge nodes requiring TLS authentication, secured firmware updates, and attested device identity.

For engineers reviewing the CYB06445LQI-S3D42 datasheet, CYB06445LQI-S3D42 pinout, CYB06445LQI-S3D42 application, or CYB06445LQI-S3D42 equivalent, key selection criteria include its pre-provisioned RoT architecture, dual-voltage core operation (0.9 V / 1.1 V), QSPI XIP with on-the-fly encryption, CAN FD interface, and 68-QFN package with 53 GPIOs including Smart I/O and OVT pins.

Technical Context

The device implements a hardened security subsystem where the Cortex-M0+ executes only immutable boot ROM and trusted services, isolating the application-running Cortex-M4F from provisioning logic and cryptographic key management. Secure boot enforces chain-of-trust via SHA-256 hash verification and ECDSA-P256 signature validation of signed images stored in flash.

Its power architecture supports six low-power modes with sub-µA quiescent current in Deep Sleep, enabled by an on-chip DC-DC buck converter and backup domain with RTC and 64-byte memory. Clocking includes IMO (8 MHz ±2%), ILO (32 kHz), PLL/FLL, and crystal oscillators (16–35 MHz & 32 kHz).

Key Specifications

Pinout & Package

68-pin QFN package (9 mm × 9 mm, 0.5 mm pitch) with exposed thermal pad; RoHS-compliant, moisture sensitivity level 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar secure MCU applications.

Compared with STM32H563VI and LPC55S69, CYB06445LQI-S3D42 delivers integrated, factory-provisioned root-of-trust with no external components, deterministic secure boot latency under 100 ms, and lower active power per MHz at sub-1V operation-critical for constrained IoT endpoints.

Availability

CYB06445LQI-S3D42 is available at Aetrix Electronics and suitable for smart home hubs, industrial sensor nodes, medical wearables, and automotive access modules requiring stable component supply, long-term lifecycle support, and certified secure boot capability.

Supply support for CYB06445LQI-S3D42 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies is a global semiconductor leader headquartered in Munich, Germany, specializing in power systems, sensors, and secure microcontrollers for industrial, automotive, and IoT markets.

The PSoC 64 product line was developed to deliver production-ready, pre-provisioned security for resource-constrained IoT endpoints-eliminating the need for third-party HSMs or custom secure boot development.

FAQ

What debug interfaces are available on CYB06445LQI-S3D42, and can they be disabled?

CYB06445LQI-S3D42 provides three debug ports: one for Cortex-M4F, one for Cortex-M0+, and a system-level SWJ interface. All are accessible via SWDIO/SWCLK pins and can be permanently disabled during final production provisioning using eFuse bits. Once locked, no debug access-including flash readout or breakpoint injection-is possible, satisfying high-assurance security requirements.

Does CYB06445LQI-S3D42 support external memory execution with encryption?

Yes. The device supports Execute-In-Place (XIP) from external quad-SPI flash with on-the-fly AES-128 decryption. A dedicated 4-KB instruction cache optimizes XIP performance while minimizing active power. Encryption keys are derived from device-unique secrets and never exposed to software, ensuring confidentiality even if external flash is physically extracted.

How is the root-of-trust implemented in hardware, and what provisioning steps are required?

The root-of-trust is implemented via immutable boot ROM, a factory-programmed public key, and a hardware SHA-256/ECC accelerator. Provisioning occurs in a certified HSM environment where OEM keys are injected into the device's secure enclave. This process generates a unique device ID and secret key, both stored in protected memory and used for attestation-no customer-side key generation or management is needed.

Can the Cortex-M0+ core be used for application code, or is it strictly reserved for security functions?

The Cortex-M0+ core is strictly reserved for system-level security services-including secure boot, cryptographic offloading, and debug policy enforcement-and is not accessible to user applications. The PSoC 64 architecture enforces this separation via hardware-enforced memory protection units (MPUs) and inter-processor communication (IPC) channels, ensuring application code running on the Cortex-M4F cannot interfere with or inspect secure services.