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Infineon Technologies CYS0644AFNI-S2D43T
- Part No.:
- CYS0644AFNI-S2D43T
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 100-UFBGA, WLCSP
- Datasheet:
-
CYS0644AFNI-S2D43T.pdf
- Description:
- IC MCU
- Quantity:
- Payment:
- Shipping:
Inventory:4,827
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Product details
Overview
CYS0644AFNI-S2D43T from Infineon is a PSOC™ 64 "Standard Secure" Arm®-based dual-core MCU featuring a 150-MHz Cortex®-M4F CPU and 100-MHz Cortex®-M0+ CPU, 1856-KB flash, 944-KB SRAM, and hardware root-of-trust for AWS-connected secure IoT endpoints. It supports Amazon FreeRTOS with PSA Level-2 compliance and executes-in-place from external QSPI flash.
For engineers reviewing the CYS0644AFNI-S2D43T datasheet, CYS0644AFNI-S2D43T pinout, CYS0644AFNI-S2D43T application, or CYS0644AFNI-S2D43T equivalent, key selection criteria include dual-core power efficiency (27 µA/MHz @ 0.9 V M4), secure boot with ECC signature validation, QSPI XIP with on-the-fly encryption, and 100 GPIOs with Smart I/O™ in Deep Sleep.
Technical Context
This MCU implements a hardened security architecture where the M0+ core is reserved exclusively for secure system functions-including Trusted Firmware-M (TF-M) SPE-and is not user-accessible. The M4 core runs application code with MPU-enforced memory isolation and integrates a cryptography accelerator supporting AES, ECC, SHA, and TRNG.
The device uses a flexible clocking system with two PLLs, an FLL, and integer/fractional peripheral dividers to independently scale CPU, bus, and peripheral clocks. Its SMIF interface delivers up to 640 Mbps throughput across single/dual/quad/octal SPI modes while maintaining 4-KB cache and XIP capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 150-MHz Arm® Cortex®-M4F + 100-MHz Cortex®-M0+, with M0+ dedicated to secure firmware execution only |
| Memory | 1856-KB application flash (RWW), 32-KB AUXflash, 32-KB SFlash, 944-KB SRAM across three retention-controllable blocks |
| Security | Immutable boot ROM, ECC-based image signature validation, PSA Level-2 certified TF-M SPE, unique device ID & secret key generation |
| QSPI/SMIF | Up to 640 Mbps throughput; supports XIP, on-the-fly AES-128 encryption/decryption, 4-KB cache, octal interface mode |
| Power Efficiency | 7 µA Deep Sleep current with 64-KB SRAM retention; 27 µA/MHz active current @ 0.9 V core for M4 core |
| Peripherals | 13 configurable SCBs (SPI/I²C/UART), USB Full-Speed, 2x SD/eMMC controllers, 32x TCPWMs, CAPSENSE™ sigma-delta, 12-bit 2-Msps SAR ADC |
Pinout & Package
Package: 100-ball Wafer-Level Chip Scale Package (WLCSP), 0.4-mm pitch, 4.2 mm × 4.2 mm footprint, bottom-side solder balls.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDIO0–VDDIO5 | I/O power supply rails | Independent 1.7–3.6 V domains per bank; enable mixed-voltage interfacing and selective power gating |
| VDDD | Digital core supply | Supplies M4/M0+ cores and digital logic; supports dynamic voltage scaling between 0.9 V and 1.1 V |
| VCCD | DC-DC converter output | On-chip buck regulator output (<1 µA quiescent); powers VDDD and reduces external supply burden |
| XRES | External reset input | Active-low asynchronous reset; internally pulled up; compatible with open-drain or push-pull drivers |
| TCK/TMS/TDI/TDO | JTAG/SWD debug interface | SWJ-DP compliant; supports full boundary scan, flash programming, and real-time trace via SWO |
Key Features
| Feature | Design Value |
|---|---|
| Secure Boot Architecture | Immutable ROM bootloader validates signed application images using ECDSA-P256; supports flexible chain-of-trust with multiple signature keys |
| Smart I/O™ in Deep Sleep | Two 16-pin Smart I/O blocks execute Boolean logic (AND/OR/XOR) on GPIOs without waking CPUs-enabling low-power sensor preprocessing |
| QSPI XIP with Encryption | Execute code directly from external flash with hardware-accelerated AES-128 decryption; eliminates RAM copy overhead and improves boot latency |
| PSA Certified TF-M SPE | Pre-built, production-ready Trusted Firmware-M binary implementing PSA RoT services (crypto, attestation, secure storage) validated to PSA Level-2 |
| Dynamic Voltage Scaling | Runtime-selectable 0.9 V / 1.1 V core voltage; reduces active power by ~30% at 150 MHz M4 operation without performance loss |
Applications
| Smart Home Hub | Industrial Edge Sensor Node |
|---|---|
Use Scenario: Local aggregation and TLS-secured MQTT forwarding of BLE/Zigbee sub-device data to AWS IoT Core. IC Role / Device Role / Timing Role: Dual-core application processor (M4) + secure enclave (M0+) handling crypto offload, OTA update verification, and device attestation. Use Value: PSA Level-2 compliance enables out-of-box AWS IoT Device Defender integration; QSPI XIP reduces BOM cost by eliminating external RAM. | Use Scenario: Battery-powered vibration/temperature monitor with predictive maintenance analytics and encrypted over-the-air firmware updates. IC Role / Device Role / Timing Role: Low-power host MCU managing PDM microphone, SAR ADC, and SD card logging while maintaining secure boot chain during field updates. Use Value: 7 µA Deep Sleep with 64-KB SRAM retention extends 10-year battery life; hardware TRNG and ECC accelerate TLS handshake by 4× vs software-only. |
| Medical Wearable Gateway | Connected Building Controller |
Use Scenario: HIPAA-compliant BLE-to-WiFi bridge collecting ECG/SpO₂ data from clinical-grade sensors and encrypting payloads before cloud upload. IC Role / Device Role / Timing Role: Secure runtime environment for cryptographic key isolation, sensor fusion on M4, and CAPSENSE™ proximity wake-up triggering. Use Value: On-chip eFuse array stores OEM root keys; Smart I/O™ detects button press in Deep Sleep at <1 µA, eliminating external wake-up circuitry. | Use Scenario: HVAC controller with BACnet/IP stack, LCD display, and tamper-resistant firmware updates via signed AFR OTA agent. IC Role / Device Role / Timing Role: Main control MCU executing real-time PID loops on M4 while M0+ enforces secure boot and validates firmware signatures pre-load. Use Value: Segment LCD driver supports 101-segment displays without external glass drivers; immutable boot prevents ransomware-style firmware corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core secure MCU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| RP2350A-QFN40 | Single-core Arm® Cortex®-M33 @ 150 MHz; no M0+ companion core; lacks integrated DC-DC; 2 MB flash, 512 KB SRAM | No hardware-enforced secure partitioning; relies on software TEE; no PSA Level-2 certification; requires external PMIC | Select when cost-sensitive designs prioritize raw compute over certified secure separation and require larger flash than CYS0644AFNI-S2D43T offers. |
| STM32H563VI | Dual-core (M33 + M33), 250 MHz M33, 2 MB flash, 1 MB SRAM; TrustZone-based security; no built-in QSPI XIP encryption engine | Requires external AES co-processor for encrypted XIP; lacks Smart I/O™; higher active current (38 µA/MHz @ 1.1 V) | Select when maximum clock speed and SRAM capacity outweigh need for ultra-low Deep Sleep current and hardware-accelerated QSPI decryption. |
Compared with RP2350A-QFN40 and STM32H563VI, CYS0644AFNI-S2D43T uniquely combines PSA Level-2 certified dual-core separation, on-die DC-DC, and QSPI XIP encryption-enabling secure AWS-connected devices with minimal external components and lowest active/deep-sleep power envelope.
Availability
CYS0644AFNI-S2D43T is available at Aetrix Electronics and suitable for smart home hubs, industrial edge sensor nodes, medical wearable gateways, and connected building controllers requiring stable component supply and long-term lifecycle support.
Supply support for CYS0644AFNI-S2D43T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and secure microcontrollers, with global R&D centers and ISO/TS 16949-certified manufacturing.
The PSOC™ 64 product line targets AWS-integrated secure IoT endpoints, delivering pre-validated PSA Level-2 security, Amazon FreeRTOS integration, and hardware-accelerated cryptography for rapid time-to-market in regulated environments.
FAQ
What is the function of the Cortex®-M0+ core in CYS0644AFNI-S2D43T?
The Cortex®-M0+ core is reserved exclusively for secure system functions and runs the Trusted Firmware-M (TF-M) Secure Processing Environment. It is not accessible to user applications and handles cryptographic operations, secure boot validation, attestation, and trusted services-ensuring strict isolation from the application-running M4 core.
Does CYS0644AFNI-S2D43T support Execute-In-Place from external flash?
Yes-it supports Execute-In-Place (XIP) via its Quad-SPI/SMIF interface with hardware-accelerated AES-128 on-the-fly decryption, 4-KB cache, and octal interface mode. This enables direct code execution from external flash without RAM loading, reducing memory footprint and boot latency.
How does the device achieve PSA Level-2 certification?
CYS0644AFNI-S2D43T achieves PSA Level-2 certification through its immutable ROM bootloader, ECC-based image signature validation, hardware TRNG, isolated TF-M SPE binary, and secure key provisioning flow-all validated against Arm's PSA Functional API and Threat Model requirements in production silicon.
What power modes are supported and what is the lowest achievable current?
The device supports six power modes including Active, Sleep, Deep Sleep, Hibernate, and two low-leakage variants. Deep Sleep mode draws 7 µA while retaining 64 KB of SRAM, enabled by the on-chip DC-DC converter's <1 µA quiescent current and selective power gating of non-essential peripherals and memory banks.
CYS0644AFNI-S2D43T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 100-UFBGA, WLCSP
- Series:
- PSOC™ 64
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 150MHz
- Connectivity:
- eMMC/SD/SDIO, FIFO, I2C, IrDA, LINbus, Microwire, QSPI, SmartCard, SPI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, CapSense, Crypto - AES, DMA, I2S, LCD, LVD, PMC, POR, PWM, RSA, SHA, Temp Sensor, TRNG, WDT
- Number of I/O:
- 82
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 1M x 8
- Voltage - Supply (Vcc/Vdd):
- 1.7V ~ 3.6V
- Data Converters:
- A/D 16x10b SAR, 16x12b Sigma-Delta; D/A 2x7/8b
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYS0644AFNI-S2D43T FAQ
1.How can I place an order for CYS0644AFNI-S2D43T through Aetrix?
Please submit a Request for Quotation (RFQ) for CYS0644AFNI-S2D43T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYS0644AFNI-S2D43T reliable?
The price and inventory of CYS0644AFNI-S2D43T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYS0644AFNI-S2D43T is usually 5 days.
3.What payment methods are accepted for CYS0644AFNI-S2D43T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYS0644AFNI-S2D43T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYS0644AFNI-S2D43T?
CYS0644AFNI-S2D43T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYS0644AFNI-S2D43T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYS0644AFNI-S2D43T?
For technical support, including CYS0644AFNI-S2D43T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYS0644AFNI-S2D43T requirements.
6.How does Aetrix verify that CYS0644AFNI-S2D43T is sourced from the original manufacturer or authorized distributors?
All CYS0644AFNI-S2D43T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYS0644AFNI-S2D43T meets industry standards.
7.What is the process for return or replacement of CYS0644AFNI-S2D43T?
All CYS0644AFNI-S2D43T units undergo pre-shipment inspection (PSI). If there is an issue with CYS0644AFNI-S2D43T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYS0644AFNI-S2D43T part is unused and in its original packaging.
Return procedure for CYS0644AFNI-S2D43T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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