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Infineon Technologies CYT2B93BACQ0AZEGST
- Part No.:
- CYT2B93BACQ0AZEGST
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
CYT2B93BACQ0AZEGST.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 64LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,914
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Product details
Overview
CYT2B93BACQ0AZEGST from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112-KB code-flash with RWW support, hardware crypto engine (AES-128/192/256, SHA-256/512, ECC, TRNG), and ASIL-B functional safety compliance. It targets body control modules requiring CAN FD (up to 8 channels), LIN (up to 12), and CXPI (up to 4) in 12 V automotive power domains.
For engineers reviewing the CYT2B93BACQ0AZEGST datasheet, CYT2B93BACQ0AZEGST pinout, CYT2B93BACQ0AZEGST application, or CYT2B93BACQ0AZEGST equivalent, this part delivers deterministic real-time control, secure boot with digital signature verification, synchronized multi-ADC sampling for motor sensing, and hardware-enforced memory protection across SRAM and flash using SECDED ECC.
Technical Context
The CYT2B93BACQ0AZEGST implements a tightly coupled dual-CPU architecture: the M4F handles primary application logic and signal processing with FPU and MPU, while the M0+ offloads peripheral management, security services, and inter-processor communication via dedicated hardware mailbox. Its clock system integrates IMO, ILO, ECO, WCO, PLL, and FLL with CSV supervision.
Peripheral resources include three DMA controllers (P-DMA0: 92 channels, P-DMA1: 44, M-DMA0: 4), 75×16-bit + 8×32-bit TCPWM blocks, 11 EVTGEN timers for DeepSleep wakeup, and three SAR ADCs (12-bit, 1 Msps, up to 67 external channels) with synchronized sampling capability for motor control feedback loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, enabling real-time task partitioning and security isolation |
| Flash Memory | 2112-KB code-flash + 128-KB work-flash with Read-While-Write (RWW) and dual-bank FOTA update support |
| SRAM | 256-KB with configurable retention granularity for low-power state preservation |
| Crypto Engine | Hardware-accelerated AES-128/192/256, SHA-256/512, ECC, RSA, TRNG, and GCM for secure boot and OTA authentication |
| Safety Certification | ASIL-B compliant with MPU, SMPU, PPU, SECDED ECC on SRAM/flash, and hardware watchdogs (WDT/MCWDT) |
| Automotive Interfaces | 8× CAN FD (ISO 11898-1:2015, up to 8 Mbps), 12× LIN (ISO 17987), 4× CXPI (20 kbps) |
| Analog Peripherals | 3× SAR ADCs (12-bit, 1 Msps), 67 total external channels, synchronized sampling, internal temp/voltage monitoring |
Pinout & Package
CYT2B93BACQ0AZEGST is packaged in a 144-pin LQFP (20 × 20 × 1.7 mm, 0.5-mm pitch) with exposed thermal pad. Pin functions are defined per Infineon's official package pin list and alternate function mapping (Datasheet Rev. *I, pp. 34–49).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD / VDDA | Core & Analog Power Supply | 2.7–5.5 V input; internal 1.1-V regulator supplies core; dual BOD thresholds (2.7 V / 3.0 V) ensure robust brown-out detection |
| P0[0]–P0[7] | GPIO_STD Bank 0 | Programmable digital I/O with event generation, wakeup, and Smart I/O Boolean logic support |
| CANFD0_TX / CANFD0_RX | CAN FD Channel 0 Interface | Differential bus interface compliant with ISO 11898-1:2015; supports data rates up to 8 Mbps with flexible data-rate framing |
| SWDIO / SWCLK | Serial Wire Debug Interface | Two-pin debug port supporting full JTAG/SWD access, ETM instruction/data trace, and secure firmware programming |
| XTAL_IN / XTAL_OUT | External Crystal Oscillator Input/Output | Supports 1–25 MHz crystals for precise clock source; used with PLL/FLL for system clock generation |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Hardware IPC | Dedicated mailbox and semaphore units enable zero-copy, low-latency inter-processor messaging without software polling |
| Firmware Update Support | Dual-bank flash architecture with RWW allows atomic over-the-air (FOTA) updates without runtime interruption |
| Motor Control Timing | 75×16-bit + 8×32-bit TCPWM blocks with dead-time insertion, quadrature decoding, and synchronized ADC triggering |
| Secure Boot Enforcement | HSM-based fast secure boot verifies ECDSA-signed firmware images before execution; prevents unauthorized code loading |
| Low-Power Wakeup Flexibility | Up to 152 GPIO pins support Sleep mode wakeup; two dedicated pins enable Hibernate wakeup with sub-μA current draw |
Applications
| Body Control Module (BCM) | Roof Module |
|---|---|
Use Scenario: Centralized control of door locks, window lifts, lighting, and seat position memory in 12 V vehicle architectures. IC Role / Device Role / Timing Role: Primary MCU executing real-time CAN FD communication, LIN slave coordination, and PWM-driven motor actuation. Use Value: Dual-core partitioning isolates safety-critical lock control (M0+) from UI rendering (M4F); synchronized ADC sampling enables precise current-sense for anti-pinch detection. | Use Scenario: Integrated sunroof, panoramic roof, and ambient lighting control with tilt/slide motion profiles and RGBW LED dimming. IC Role / Device Role / Timing Role: Real-time motion controller with TCPWM dead-time management and LIN-based sensor feedback aggregation. Use Value: Hardware CRC32 and SECDED ECC protect flash/SRAM against bit flips in high-vibration environments; 12-bit ADCs monitor motor coil temperature and supply voltage. |
| Front-End Junction Box | Smart Rearview Mirror |
Use Scenario: Power distribution and load switching for front-end electronics including headlights, fog lamps, and ADAS sensors. IC Role / Device Role / Timing Role: High-reliability power manager with ASIL-B fault handling, OVD/BOD monitoring, and CAN FD diagnostics reporting. Use Value: Peripheral Protection Unit (PPU) enforces hardware-level access control to GPIO and PWM registers; MCWDT ensures fail-safe shutdown on software hang. | Use Scenario: Driver assistance display with camera feed overlay, blind-spot alert, and automatic dimming based on ambient light and glare detection. IC Role / Device Role / Timing Role: Vision-adjacent controller managing I2C camera interface, PWM backlight control, and LIN-connected mirror actuators. Use Value: Smart I/O blocks perform real-time Boolean logic on ambient light sensor inputs to trigger dimming without CPU intervention; RTC maintains accurate timestamping for event logs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SPC58EC80E5 | Single-core Power Architecture (e200z4), 2 MB flash, no integrated crypto engine, ASIL-B certified via external HSM | Lacks native dual-CPU partitioning and hardware-accelerated ECC/RSA; requires external security IC for secure boot | Select when legacy Power Architecture toolchain compatibility is required and crypto offload is acceptable |
| TC377TP | Tri-core AURIX™ (2× TriCore + 1× Cortex-M3), 4 MB flash, integrated HSM, ASIL-D capable | Higher safety grade (ASIL-D), larger memory, but higher power and cost; lacks CXPI and Smart I/O features | Select for chassis/safety-critical domains where ASIL-D certification and redundancy are mandatory |
Compared with SPC58EC80E5 and TC377TP, CYT2B93BACQ0AZEGST offers balanced ASIL-B performance with integrated dual-core security, CXPI support for next-gen body networks, and Smart I/O for deterministic peripheral logic-without requiring external HSM or over-provisioned safety margins.
Availability
CYT2B93BACQ0AZEGST is available at Aetrix Electronics and suitable for body control modules, roof modules, junction boxes, and smart rearview mirrors requiring stable component supply, automotive-grade lifecycle support, and ASIL-B compliance.
Supply support for CYT2B93BACQ0AZEGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global manufacturing and automotive qualification expertise.
CYT2B93BACQ0AZEGST belongs to the TRAVEO™ T2G family, designed specifically for automotive body electronics requiring real-time responsiveness, functional safety, and integrated security without external co-processors.
FAQ
What is the maximum operating frequency of each CPU core in CYT2B93BACQ0AZEGST?
The Arm® Cortex®-M4F core operates at up to 160 MHz, delivering 200+ DMIPS performance with single-cycle multiply and hardware FPU. The Arm® Cortex®-M0+ core runs at up to 100 MHz, optimized for deterministic peripheral and security task handling. Both cores derive clocks from independent PLL/FLL paths with CSV supervision to prevent timing faults.
Does CYT2B93BACQ0AZEGST support Over-The-Air (OTA) firmware updates?
Yes. It supports atomic OTA updates via dual-bank flash architecture with Read-While-Write capability. Code-flash and work-flash allow one bank to execute while the other is reprogrammed. Secure boot validates ECDSA signatures before activation, ensuring only authenticated firmware runs after update completion.
How many CAN FD channels does CYT2B93BACQ0AZEGST implement, and what is their compliance status?
CYT2B93BACQ0AZEGST implements up to eight CAN FD channels compliant with ISO 11898-1:2015 and Bosch CAN FD Specification V1.0. It holds ISO 16845:2015 conformance certification for physical layer interoperability testing, supporting data rates up to 8 Mbps depending on transceiver and topology constraints.
What safety mechanisms are implemented to meet ASIL-B requirements?
ASIL-B compliance is achieved through hardware-enforced mechanisms: Memory Protection Unit (MPU) and Shared MPU (SMPU) for memory region isolation, Peripheral Protection Unit (PPU) for register access control, SECDED ECC on all SRAM and flash, dual-threshold Brown-Out Detection (BOD), Clock Supervision (CSV), and redundant watchdogs (WDT + MCWDT) with independent clock sources.
CYT2B93BACQ0AZEGST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 64-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 49
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 45x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B93BACQ0AZEGST FAQ
1.How can I place an order for CYT2B93BACQ0AZEGST through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B93BACQ0AZEGST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B93BACQ0AZEGST reliable?
The price and inventory of CYT2B93BACQ0AZEGST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B93BACQ0AZEGST is usually 5 days.
3.What payment methods are accepted for CYT2B93BACQ0AZEGST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B93BACQ0AZEGST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B93BACQ0AZEGST?
CYT2B93BACQ0AZEGST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B93BACQ0AZEGST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B93BACQ0AZEGST?
For technical support, including CYT2B93BACQ0AZEGST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B93BACQ0AZEGST requirements.
6.How does Aetrix verify that CYT2B93BACQ0AZEGST is sourced from the original manufacturer or authorized distributors?
All CYT2B93BACQ0AZEGST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B93BACQ0AZEGST meets industry standards.
7.What is the process for return or replacement of CYT2B93BACQ0AZEGST?
All CYT2B93BACQ0AZEGST units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B93BACQ0AZEGST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B93BACQ0AZEGST part is unused and in its original packaging.
Return procedure for CYT2B93BACQ0AZEGST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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