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Infineon Technologies CYT2B93BACQ0AZSGST
- Part No.:
- CYT2B93BACQ0AZSGST
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
CYT2B93BACQ0AZSGST.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 64LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,149
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Product details
Overview
CYT2B93BACQ0AZSGST from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112-KB code-flash with RWW support, 256-KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration including AES-128/192/256, SHA-256/512, and ECC.
For engineers reviewing the CYT2B93BACQ0AZSGST datasheet, CYT2B93BACQ0AZSGST pinout, CYT2B93BACQ0AZSGST application, or CYT2B93BACQ0AZSGST equivalent, this part delivers deterministic real-time control, hardware-enforced security isolation between cores, and fine-grained low-power states (Hibernate, DeepSleep) for automotive ECU designs with strict safety and update-over-the-air (FOTA) requirements.
Technical Context
The device implements hardware inter-processor communication (IPC) between M4F and M0+ subsystems, enabling secure peripheral offloading and asymmetric processing. Its memory subsystem includes SECDED ECC on all safety-critical SRAM and flash, SMPU for shared resource protection, and PPU for peripheral access control.
Clock architecture integrates IMO, ILO, ECO, WCO, PLL, and FLL with CSV supervision; analog subsystem features three SAR ADCs (12-bit, 1 Msps) with synchronized sampling and motor-control-optimized channel routing via AMUXBUS and dedicated motor-sense I/Os.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, with hardware IPC and independent MPUs |
| Flash Memory | 2112-KB code-flash + 128-KB work-flash; supports Read-While-Write and dual-bank FOTA updates |
| SRAM | 256-KB with configurable retention granularity per memory region |
| Crypto Engine | HSM-compliant with AES-128/192/256, SHA-256/512, ECC, RSA, TRNG, and GCM mode |
| Automotive Interfaces | 8× CAN FD (ISO 11898-1:2015 compliant, up to 8 Mbps), 12× LIN (ISO 17987), 4× CXPI (20 kbps) |
| Safety Certification | ASIL-B compliant with SECDED ECC on SRAM/flash, SMPU, PPU, MCWDT, and CSV |
| ADC System | Three 12-bit SAR ADCs (ADC0–ADC2) supporting 67 total external channels and synchronized sampling for motor control |
Pinout & Package
Package: 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch), RoHS-compliant, automotive-grade (AEC-Q100 Grade 2).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDA, VDDD, VCCD | Analog/Digital/Core Power Supplies | Independent 2.7–5.5-V inputs with BOD thresholds at 2.7 V / 3.0 V (VDDD/VDDA) and 1.1 V (VCCD) |
| P0[0]–P11[7] | Programmable GPIO (152 total) | Two types: GPIO_STD (standard drive) and GPIO_ENH (enhanced with Smart I/O Boolean logic) |
| CANFD0_TX/RX – CANFD7_TX/RX | CAN FD Transceiver Interfaces | Dedicated differential pairs per channel; each supports ISO 11898-1:2015 and Bosch CAN FD v1.0 |
| LIN0–LIN11 | Local Interconnect Network Outputs | 12 independent LIN PHY outputs compliant with ISO 17987; each supports slave node auto-addressing |
| CXPI0–CXPI3 | Clock Extension Peripheral Interface | 4 single-wire bidirectional channels operating at 20 kbps for low-cost sensor/actuator networks |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Security Partitioning | M0+ handles secure boot, crypto key management, and peripheral offload; M4F runs application firmware with MPU-enforced isolation |
| FOTA-Ready Flash Architecture | Dual-bank flash enables atomic firmware swaps without runtime interruption; RWW allows background updates during active execution |
| Motor-Control ADC Synchronization | Three SAR ADCs trigger simultaneously via hardware event generator for precise rotor position sensing in BLDC/PMSM drives |
| Smart I/O Logic Blocks | Five programmable logic units perform real-time Boolean operations (AND/OR/XOR) on GPIO signals-no CPU intervention required |
| Low-Power Wake-Up Flexibility | Hibernate wakeup via 2 pins; Sleep wakeup via any of 152 GPIOs; DeepSleep wakeup via EVTGEN timers, RTC alarms, or SCB events |
Applications
| Body Control Module (BCM) | Door Module Controller |
|---|---|
Use Scenario: Centralized control of lighting, window lifts, mirrors, locks, and interior sensors in modern vehicle door assemblies. IC Role / Device Role / Timing Role: Primary MCU executing LIN slave protocol stacks, PWM-driven motor control for window regulators, and secure CAN FD gateway functions. Use Value: Integrated LIN transceivers eliminate external PHYs; Smart I/O reduces need for discrete logic; ASIL-B safety enables functional integration without external monitors. | Use Scenario: Real-time coordination of power window, mirror fold/unfold, and anti-pinch detection using analog current sensing and encoder feedback. IC Role / Device Role / Timing Role: Dual-core execution: M0+ manages safety-critical current monitoring and emergency stop logic; M4F runs PID motor control and LIN communication. Use Value: Synchronized triple ADC sampling captures simultaneous phase currents and bus voltage; hardware ECC ensures integrity of stored calibration data. |
| Roof Module Controller | Seat Control Unit |
Use Scenario: Managing sunroof actuation, ambient lighting zones, and rain/light sensors with coordinated dimming and obstruction detection. IC Role / Device Role / Timing Role: Real-time PWM generation for LED drivers, SAR ADC acquisition of photodiode/sensor inputs, and CAN FD reporting of status and faults. Use Value: 12-bit ADC resolution and 1 Msps sampling enable precise lux-level differentiation; low-power DeepSleep modes extend battery life during vehicle sleep. | Use Scenario: Controlling seat position motors, heating elements, and occupancy detection via capacitive sensing and thermistor readings. IC Role / Device Role / Timing Role: Secure crypto engine authenticates OTA seat profile updates; dedicated TCPWM blocks generate dead-time-corrected motor drive signals. Use Value: Hardware AES-GCM encrypts firmware images; PWM_DT mode prevents shoot-through in H-bridge drivers; eSHE/HSM compliance satisfies OEM cybersecurity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| S32K344WAT0VLHT | NXP S32K344: 300-MHz Arm® Cortex®-M7 + M7 lockstep, 4 MB flash, AURIX™-class ASIL-D support, no CXPI | Targets higher-ASIL domains (e.g., chassis control); lacks CXPI but adds Ethernet TSN and more CAN FD channels | Select when ASIL-D certification, time-sensitive networking, or larger code footprint is required over CXPI integration |
| TC397XP-128F300S-AC | Infineon AURIX™ TC397: Tri-core lockstep (2× M7 + 1× M7), 8 MB flash, 12 MB RAM, no LIN/CXPI, higher core count | Designed for domain controllers and ADAS fusion; no LIN/CXPI support but superior compute density and safety redundancy | Select for centralized ECU consolidation where LIN/CXPI are absent and lockstep M7 performance dominates cost/power trade-offs |
Compared with S32K344 and TC397, CYT2B93BACQ0AZSGST offers optimal balance of dual-core flexibility, integrated LIN/CXPI for cost-sensitive body electronics, and certified ASIL-B safety-without over-provisioning compute or memory for non-domain-controller roles.
Availability
CYT2B93BACQ0AZSGST is available at Aetrix Electronics and suitable for body control modules, door module controllers, roof module controllers, and seat control units requiring stable component supply, automotive qualification (AEC-Q100 Grade 2), and long-term lifecycle support.
Supply support for CYT2B93BACQ0AZSGST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global manufacturing and automotive qualification infrastructure.
CYT2B9 belongs to the TRAVEO™ T2G family, designed specifically for automotive body electronics requiring integrated communication (CAN FD/LIN/CXPI), hardware security (HSM/eSHE), and functional safety (ASIL-B) in cost-optimized LQFP packages.
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CYT2B93BACQ0AZSGST?
The Arm® Cortex®-M4F core operates at up to 160 MHz, confirmed in the official Infineon datasheet (Rev. *I, p.1). This frequency is achievable under full voltage and temperature conditions (AEC-Q100 Grade 2: −40°C to +105°C ambient) with appropriate clock source configuration using the internal PLL or external crystal oscillator.
Does CYT2B93BACQ0AZSGST support Over-The-Air (OTA) firmware updates?
Yes. The device supports secure OTA updates via its dual-bank flash architecture (2112-KB code-flash + 128-KB work-flash) and Read-While-Write capability. Firmware validation uses hardware-accelerated digital signature verification (RSA/ECC) and AES-GCM decryption within the HSM, ensuring authenticated and encrypted image loading without CPU intervention.
How many CAN FD channels does CYT2B93BACQ0AZSGST provide, and what is their data rate capability?
CYT2B93BACQ0AZSGST provides up to eight CAN FD channels, each compliant with ISO 11898-1:2015 and supporting data rates up to 8 Mbps. Actual achievable rate depends on physical layer topology and external transceiver selection, but the controller fully implements Bosch CAN FD Specification V1.0 for non-ISO operation and holds ISO 16845:2015 conformance certification.
Is the CYT2B93BACQ0AZSGST pin-compatible with other TRAVEO™ T2G variants?
No. CYT2B93BACQ0AZSGST uses a 176-pin LQFP package. Pin compatibility is limited to same-package variants (e.g., CYT2B93BACQ0AZSxx with identical 176-LQFP footprint), not across different pin counts (64/80/100/144/176-LQFP). Signal mapping, alternate functions, and power pin assignments differ between package options and must be verified per datasheet Table 12 and Section 10.
CYT2B93BACQ0AZSGST Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 64-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 49
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 45x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B93BACQ0AZSGST FAQ
1.How can I place an order for CYT2B93BACQ0AZSGST through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B93BACQ0AZSGST on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B93BACQ0AZSGST reliable?
The price and inventory of CYT2B93BACQ0AZSGST are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B93BACQ0AZSGST is usually 5 days.
3.What payment methods are accepted for CYT2B93BACQ0AZSGST?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B93BACQ0AZSGST transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B93BACQ0AZSGST?
CYT2B93BACQ0AZSGST orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B93BACQ0AZSGST order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B93BACQ0AZSGST?
For technical support, including CYT2B93BACQ0AZSGST datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B93BACQ0AZSGST requirements.
6.How does Aetrix verify that CYT2B93BACQ0AZSGST is sourced from the original manufacturer or authorized distributors?
All CYT2B93BACQ0AZSGST products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B93BACQ0AZSGST meets industry standards.
7.What is the process for return or replacement of CYT2B93BACQ0AZSGST?
All CYT2B93BACQ0AZSGST units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B93BACQ0AZSGST, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B93BACQ0AZSGST part is unused and in its original packaging.
Return procedure for CYT2B93BACQ0AZSGST:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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