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Infineon Technologies CYT2B94BACQ0AZSGS
- Part No.:
- CYT2B94BACQ0AZSGS
- Manufacturer:
- Infineon Technologies
- Category:
- Microcontrollers
- Package:
- 80-LQFP
- Datasheet:
-
CYT2B94BACQ0AZSGS.pdf
- Description:
- IC MCU 32BT 2.0625MB FLSH 80LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,544
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Product details
Overview
CYT2B94BACQ0AZSGS from Infineon is a dual-core automotive microcontroller featuring a 160-MHz Arm® Cortex®-M4F CPU and a 100-MHz Arm® Cortex®-M0+ CPU, 2112 KB code-flash with RWW support, 256 KB SRAM, and integrated CAN FD (up to 8 channels), LIN (up to 12 channels), and CXPI (up to 4 channels). It targets body control modules requiring ASIL-B functional safety, secure boot, and hardware crypto acceleration (AES-128/192/256, SHA-256/512, ECC, TRNG).
For engineers reviewing the CYT2B94BACQ0AZSGS datasheet, CYT2B94BACQ0AZSGS pinout, CYT2B94BACQ0AZSGS application, or CYT2B94BACQ0AZSGS equivalent, this part delivers deterministic real-time control, hardware-enforced memory protection (MPU/SMPU), synchronized multi-ADC sampling for motor sensing, and low-power DeepSleep/Hibernate modes with configurable wake-up sources including GPIO, RTC, and EVTGEN timers.
Technical Context
The CYT2B94BACQ0AZSGS implements a tightly coupled dual-CPU architecture: the M4F handles primary application tasks with FPU and single-cycle multiply, while the M0+ manages peripheral offload, security services, and inter-processor communication via dedicated hardware mailbox. Its clock system integrates IMO, ILO, ECO, WCO, PLL, and FLL with dynamic frequency scaling across power modes.
Peripheral subsystems include three DMA controllers (P-DMA0: 92 channels, P-DMA1: 44 channels, M-DMA0: 4 channels), 75×16-bit + 8×32-bit TCPWM blocks supporting PWM_DT and quadrature decoding, and three SAR ADCs (12-bit, 1 Msps) with synchronized sampling and external multiplexer addressing-enabling precise motor current/voltage monitoring in automotive body electronics.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160-MHz Arm® Cortex®-M4F + 100-MHz Arm® Cortex®-M0+, enabling real-time task partitioning and security isolation |
| Flash Memory | 2112 KB code-flash + 128 KB work-flash, supporting Read-While-Write and dual-bank firmware updates for FOTA |
| SRAM | 256 KB with selectable retention granularity, allowing selective memory retention during low-power Sleep modes |
| CAN FD Channels | Up to 8 channels compliant with ISO 11898-1:2015 and Bosch CAN FD v1.0, enabling 8 Mbps data rates for high-bandwidth body network messaging |
| ADC System | Three 12-bit SAR ADCs (ADC0–ADC2) with up to 67 total external channels and synchronized sampling for motor-sense applications |
| Crypto Engine | HSM-compliant engine supporting AES-128/192/256, SHA-256/512, ECC, RSA, TRNG, and GCM for secure boot and OTA authentication |
| Functional Safety | ASIL-B compliant with SECDED ECC on SRAM/flash, MPU/SMPU, PPU, MCWDT, and BOD/LVD/OVD voltage supervision |
Pinout & Package
CYT2B94BACQ0AZSGS is packaged in a 176-pin LQFP (24 × 24 × 1.7 mm, 0.5-mm pitch) with dedicated power, ground, analog, high-speed digital, and debug pins. Pin functions are defined per package variant in Infineon's official pin list (Datasheet Rev. *I, Section 12).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDDD / VDDA / VCCD | Core, Analog, and Digital Power Supplies | Separate regulated domains enable noise isolation between digital logic, analog converters, and CPU core; VCCD supports 1.1-V core rail derived from 2.7–5.5-V input |
| P0.0–P11.7 (152 total) | Programmable GPIO (STD/ENH) | Configurable as digital I/O, analog inputs, or peripheral alternate functions (CAN FD, LIN, CXPI, SCB); up to 152 pins support wake-up from Sleep modes |
| TCK/TMS/TDO/TDI / SWDIO/SWCLK | JTAG/SWD Debug Interface | IEEE-1149.1-compliant JTAG and Arm SWD ports support full-chip debugging, flash programming, and ETM instruction/data trace |
| CANFD0_TX/RX – CANFD7_TX/RX | CAN FD Transceiver Interfaces | Dedicated differential pairs per channel; each supports ISO 11898-1 physical layer compliance and runtime reconfiguration |
| ADC0_IN0–ADC2_INn | Analog Input Channels | Physical pins mapped to logical ADC channels via AMUXBUS; support simultaneous sampling across all three ADCs for motor phase current/voltage capture |
Key Features
| Feature | Design Value |
|---|---|
| Dual-CPU Inter-Processor Communication | Hardware mailbox with interrupt signaling enables deterministic, lock-free message passing between M4F and M0+ without software polling overhead |
| Firmware Update Over The Air (FOTA) | Dual-bank flash architecture with RWW allows background firmware validation and atomic bank swap-critical for zero-downtime vehicle software updates |
| Synchronized Multi-ADC Sampling | Three SAR ADCs triggered simultaneously by shared event source, eliminating timing skew in motor current sensing for field-oriented control (FOC) |
| Smart I/O Logic Blocks | Five programmable logic units perform Boolean operations (AND/OR/XOR) on GPIO signals in hardware-offloading timing-critical signal conditioning from CPU |
| DeepSleep Wake-Up Sources | 11 EVTGEN timers generate cyclic interrupts from DeepSleep mode, enabling periodic sensor polling or CAN bus heartbeat without full CPU wake-up |
Applications
| Body Control Module (BCM) | Door Module Controller |
|---|---|
|
Use Scenario: Centralized management of lighting, window lift, mirror adjustment, and door lock actuation in modern vehicles. IC Role / Device Role / Timing Role: Primary MCU executing real-time control loops, CAN FD gatewaying, and LIN slave coordination across distributed nodes. Use Value: Dual-core partitioning isolates safety-critical door lock logic (M0+) from infotainment-linked lighting features (M4F), meeting ASIL-B requirements while reducing BOM count. |
Use Scenario: Local control of power windows, side mirrors, and interior lighting within individual vehicle doors. IC Role / Device Role / Timing Role: LIN master node communicating with BCM over LIN bus; executes local PWM motor control and touch-sensing algorithms. Use Value: Integrated 12-bit ADCs with synchronized sampling enable precise current-based anti-pinch detection using motor winding voltage/current measurements. |
| Roof Module Controller | Seat Control Unit |
|
Use Scenario: Managing sunroof position, ambient lighting zones, and rain sensor integration in roof console assemblies. IC Role / Device Role / Timing Role: CAN FD endpoint collecting sensor data and driving RGB LED drivers via PWM_DT outputs with dead-time control. Use Value: Smart I/O blocks implement hardware-based fade-in/fade-out logic for smooth LED transitions-reducing CPU load and jitter in lighting control. |
Use Scenario: Controlling seat position motors, heating elements, and occupancy detection sensors in driver/passenger seats. IC Role / Device Role / Timing Role: Motor control MCU performing FOC using synchronized ADC sampling of three-phase currents and Hall sensor inputs. Use Value: 75×16-bit TCPWM blocks provide independent PWM generation with programmable dead time for six-step commutation and regenerative braking control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| NXP S32K344 | Single 240-MHz Arm® Cortex®-M7 core; no companion M0+; includes HSE security module but lacks integrated CXPI | Targets higher-performance chassis/safety domains; requires external LIN/CXPI transceivers | Select when prioritizing raw M7 compute throughput over hardware-isolated peripheral/security processing |
| Renesas RH850/U2A | 32-bit RXv3 core (not Arm); 480-MHz max; supports CAN FD and LIN but no native CXPI; uses different crypto IP (TRUSTZONE-based) | Used in Japanese OEM powertrain systems; toolchain and ecosystem differ significantly from Arm-based workflows | Select for legacy RH850 platform continuity or where non-Arm ISA alignment is mandated |
Compared with NXP S32K344 and Renesas RH850/U2A, CYT2B94BACQ0AZSGS uniquely combines Arm dual-core determinism, native CXPI support for next-gen body networks, and hardware-synchronized triple ADC sampling-making it optimal for cost-sensitive, ASIL-B-compliant body domain controllers requiring mixed-signal precision and secure FOTA.
Availability
CYT2B94BACQ0AZSGS is available at Aetrix Electronics and suitable for automotive body control modules, door module controllers, roof console systems, and seat control units requiring stable component supply, long lifecycle support, and ASIL-B compliance.
Supply support for CYT2B94BACQ0AZSGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies is a German semiconductor manufacturer specializing in power management, automotive ICs, and security solutions, with global R&D and manufacturing infrastructure.
CYT2B94BACQ0AZSGS belongs to the TRAVEO™ T2G family-designed specifically for automotive body electronics requiring real-time responsiveness, functional safety (ASIL-B), hardware-accelerated security, and multi-protocol connectivity (CAN FD/LIN/CXPI).
FAQ
What is the maximum operating frequency of the Cortex-M4F core in CYT2B94BACQ0AZSGS?
The Arm® Cortex®-M4F core operates at up to 160 MHz, verified in the device's electrical specifications (Datasheet Rev. *I, Section 27.11). This frequency is achievable under specified voltage (2.7–5.5 V) and temperature (–40°C to +125°C) conditions, with PLL clock source enabled and appropriate voltage regulator configuration.
Does CYT2B94BACQ0AZSGS support hardware-based secure boot with cryptographic verification?
Yes-it implements fast secure boot using digital signature verification (ECDSA or RSA) via its integrated Hardware Security Module (HSM). Boot image authenticity is validated against public keys stored in eFuse before execution, with AES-GCM decryption applied to encrypted firmware images loaded into flash.
How many CAN FD channels are physically implemented in the 176-LQFP package of CYT2B94BACQ0AZSGS?
All CYT2B9 variants-including the 176-LQFP CYT2B94BACQ0AZSGS-support up to eight CAN FD channels, as confirmed in the feature list (Datasheet Rev. *I, Table 1-1) and peripheral I/O map (Section 7). Each channel has dedicated TX/RX pins routed to the package's high-speed I/O banks.
Is the 256 KB SRAM in CYT2B94BACQ0AZSGS fully retained in DeepSleep mode?
No-SRAM retention is configurable per 8-KB block. In DeepSleep mode, only selected blocks retain data; full retention requires Hibernate mode. This granular control minimizes leakage current while preserving critical context (e.g., CAN message buffers or calibration data) without powering the entire memory array.
CYT2B94BACQ0AZSGS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Package/Case:
- 80-LQFP
- Series:
- Traveo™ T2G
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+, ARM® Cortex®-M4F
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 100MHz, 160MHz
- Connectivity:
- CANbus, FIFO, I2C, IrDA, LINbus, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, Crypto - AES, DMA, LVD, POR, PWM, SHA, TRNG, WDT
- Number of I/O:
- 63
- Program Memory Size:
- 2.0625MB (2.0625M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 128K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.7V ~ 5.5V
- Data Converters:
- A/D 52x12b SAR
- Oscillator Type:
- External, Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
CYT2B94BACQ0AZSGS FAQ
1.How can I place an order for CYT2B94BACQ0AZSGS through Aetrix?
Please submit a Request for Quotation (RFQ) for CYT2B94BACQ0AZSGS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for CYT2B94BACQ0AZSGS reliable?
The price and inventory of CYT2B94BACQ0AZSGS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for CYT2B94BACQ0AZSGS is usually 5 days.
3.What payment methods are accepted for CYT2B94BACQ0AZSGS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for CYT2B94BACQ0AZSGS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for CYT2B94BACQ0AZSGS?
CYT2B94BACQ0AZSGS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your CYT2B94BACQ0AZSGS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for CYT2B94BACQ0AZSGS?
For technical support, including CYT2B94BACQ0AZSGS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your CYT2B94BACQ0AZSGS requirements.
6.How does Aetrix verify that CYT2B94BACQ0AZSGS is sourced from the original manufacturer or authorized distributors?
All CYT2B94BACQ0AZSGS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that CYT2B94BACQ0AZSGS meets industry standards.
7.What is the process for return or replacement of CYT2B94BACQ0AZSGS?
All CYT2B94BACQ0AZSGS units undergo pre-shipment inspection (PSI). If there is an issue with CYT2B94BACQ0AZSGS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The CYT2B94BACQ0AZSGS part is unused and in its original packaging.
Return procedure for CYT2B94BACQ0AZSGS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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